ISPD 2026 Program

1. "Technology-Aware 3D Placement with ILP-Based Region Planning for Soft Modules", Cheng-Xun Song, Minh Anh Phan, Sheng-Tan Huang, Shao-Yun Fang, Tung-Chieh Chen, Kai-Shun Hu and Chin-Fang Cindy Shen (National Taiwan University of Science and Technology, Synopsys)

2. "IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs", Zixian Yang, Shanyi Li, Leilei Jin, Tsung-Yi Ho and Chien-Nan Liu (National Yang Ming Chiao Tung University, The Chinese University of Hong Kong)

3. "Multi-Level Interconnect Planning for Signal-Power-Thermal Integrity in 2.5D/3D Integration", Siyuan Miao, Lingkang Zhu, Xiangqiao Meng, Wenkai Yang, Chengyu Zhu, Chen Wu and Lei He (University of California, Los Angeles, The Hong Kong Polytechnic University, Shanghaitech University, BTD Technology Inc., Ningbo Institute of Digital Twin, Eastern Institute of Technology)

1. "Photonics-Aware Planning-Guided Automated Electrical Routing for Large-Scale Active Photonic Integrated Circuits", Hongjian Zhou, Haoyu Yang, Nicholas Gangi, Bowen Liu, Meng Zhang, Haoxing Ren, Xu Wang, Rena Huang and Jiaqi Gu (Arizona State University, NVIDIA, Rensselaer Polytechnic Institute, Cadence)

2. "Invited: Navigating the Frontier of Optimality and Complexity: Advanced Design Automation for Wavelength-Routed ONoCs", Ulf Schlichtmann (Technical University of Munich)

3. "Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware Reservation", Hsin-Tzu Chang, Iris Hui-Ru Jiang, Hua-Yu Chang and Chun-Hao Lai (National Taiwan University, Synopsys)

1. "Gradient-Guided RC Weighting for Timing-Driven Global Routing", Liang Xiao, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F.Y. Young and Martin Wong (The Chinese University of Hong Kong, Hong Kong Baptist University)

2. "GrandPlan: Differentiable, Simultaneous Top-Level Floorplanning and Partition-Level Cell Placement for Large-Scale IP-Cores", Zhili Xiong, Yi-Chen Lu, David Z. Pan and Haoxing Ren (The University of Texas at Austin, NVIDIA)

3. "Invited: BonnRoute: Classic Routing Algorithms with Recent Advances", Jens Vygen (University of Bonn)

1. "A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library Synthesis", Meng-Yu Shih, Ting-Xin Lin and Yih-Lang Li (National Yang Ming Chiao Tung University)

2. "TransOpt: A Scalable Transistor-Level Placement and Routing Optimization Framework Beyond Standard Cells", Chen-Hao Hsu and David Z. Pan (University of Texas at Austin)

3. "A New Approach to Performance-Driven Analog IC Placement", Donghao Fang, Hailiang Hu, Wuxi Li and Jiang Hu (Texas A&M University, AMD)

4. "Invited: Physical Synthesis/Layout Issues Specific to FPGA-based Emulation and Prototyping", Helena Krupnova (Synopsys)

Thomas Andersen (Synopsys)
Bei Yu (The Chinese University of Hong Kong)
Mark Ho (Nvidia)
Ankur Gupta (Siemens)
Andrew Kahng (University of California, San Diego)

1. "AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter Tuner", Runzhi Wang, Jingyu Pan, Yiran Chen and Jiang Hu (Texas A&M University, Duke University)

2. "CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization", Shixin Chen, Hengyuan Zhang, Jianwang Zhai and Bei Yu (The Chinese University of Hong Kong, Beijing University of Posts and Telecommunications)

3. "Invited: Bidirectional Data Flow in VLSI Design Using Ontology and Knowledge Graph", Ilhami Torunoglu (Siemens)

1. "Invited: Improving Runtime Scaling in the EDA Flow for Designs with Millions of Gates", David Chinnery (Siemens)

2. "Invited: Challenges and Opportunities in Advanced-node Design Closure", Will Reece (Cadence)

3. "An Improved Ion-Shuttling Approach for QCCD Architectures", Tung-Yeh Wu and Ting-Chi Wang (National Tsing Hua University)

4. "Timing-Aware End-to-End Circuit Compilation Framework for Modular Quantum Systems", Ching-Yao Huang and Wai-Kei Mak (National Tsing Hua University)

1. "Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems", Sachin Sapatnekar (University of Minnesota)

2. "Invited: Electromigration Avoidance Strategies in Infineon", Shanthi Siemes (Infineon Technologies Dresden)

3. "Invited: Addressing Electromigration Challenges in 3D Integrated Circuit (3DIC) Wafer-On-Wafer Technology", Ingo Kühn (Global Foundries)

1. "Invited: Substrate Netlist Extraction in Analog Design", Klaus Heinrich (XFAB)

2. "Invited: Novel Concepts to Improve Custom Layout Automation Capabilities", Goeran Jerke, Thomas Burdick, Peter Herth, Vinko Marolt, Andrew Beckett (Bosch, Cadence)

3. "Invited: Analog Computation with Oscillatory Neural Networks", Aida Todri-Sanial (Eindhoven University of Technology)

4. "Invited: Analog IC Design Automation -- More than a Technical Challenge", Benjamin Prautsch (Fraunhofer EAS)

"Invited: A History of Influences", Jürgen Scheible (Reutlingen University)

"Invited: The Many PD Faces of Professor Jens Lienig", Andrew Kahng (University of California, San Diego)

"Invited: From Evolutionary Algorithms to Analog IC Design, 3D Integration, Reliability, and Beyond: On Jens Lienig's Contributions to Advance Physical Design", Johan Knechtel (New York University Abu Dhabi)

"Invited: Layout Design Automation: From Academia to Industry and Back", Jens Lienig (Dresden University of Technology)

1. "Invited: Benchmarker: A Web-Based System for Tracking Experimental Results", Rahul Rana, Tejas Bachhav, Aniruddha Dhumal, Ashutosh Pareek, Riya Sara Angel Korrapolu, Sathya Sai Ram Prabhala, Patrick Madden, Dishant Bhatnagar (Binghamton University)

2. "Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research", Liwen Jiang, Andrew Kahng, Zhiang Wang, Zhiyu Zheng (Fudan University, University of California, San Diego)

3. "Invited: Modern Hypergraph Partitioning: KaHyPar, Mt-KaHyPar, and Beyond", Sebastian Schlag, Christian Schulz, Tobias Heuer (Heidelberg University, eBay)