List of Accepted Papers

• #10 M3: Multi-objective Multi-fidelity Optimization for Chiplet Architecture Design using Multi-stage Simulation
• #11 RouteFormer: Learning-Based Incremental Timing-Driven Global Routing
• #13 Advanced Post-Placement Power and Timing Optimization Using Multi-Bit Flip-Flops
• #14 Probabilistic Legal-Row Relaxation for Hybrid-Row-Height Analytical Placement
• #25 Simple Electrostatic Global Placement without Filler Cells
• #27 Warpage-Aware Floorplanning for Embedded-Die Packaging via Material-Point-Based Framework
• #30 CoDES: Congestion-Driven Differentiable Edge Shifting for Global Routing
• #31 Post-Optimizing Multi-Bit Flip-Flop Framework by Skew-Aware Incremental Re-Merging
• #32 GradBank: Gradient-Descent-Driven Multibit Flip-Flop Banking for Power, Performance, and Area Co-Optimization
• #42 Automatic Placement Guidance Generation via Timing-Aware Graph Neural Networks
• #45 Hetero-PDN: A Cross-Tier Power Delivery Optimization Flow for Heterogeneous 3D-ICs
• #53 Differentiable Timing-Driven Hybrid Bonding Terminal Assignment for Face-to-Face Stacked 3D ICs
• #54 Learn the Solver, Not the Field: Zero-Shot Technology Transfer for Static IR Drop via Learned Multigrid Preconditioning
• #55 FuLa: An End-to-End Function-to-Layout Framework for Standard-Cell Synthesis with PPA Optimization
• #56 DRR: Differentiable Rail Routing for Modern Printed Circuit Boards with Complex Power Distribution Networks
• #74 3DCoolFloor: Thermal-Aware Floorplanning with Differentiable Microchannel Co-Design
• #78 Modern floorplanning combining by non-convex continuation and convex optimization
• #79 GLIDE: Matching and IR Drop Aware Analog Current Delivery by Differentiable Post-Route Gridless Optimization
• #83 Nested Interval Assignment for Optical Channel Yield under Rigid Alignment Errors
• #84 Beyond Minimum Demand: Exact Interval Power Sets for Optical Power Delivery Networks