List of Accepted Papers

#1 A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library Synthesis
#4 CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization
#8 A New Approach to Performance-Driven Analog IC Placement
#9 AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter Tuner
#15 TransOpt: A Scalable Transistor-Level Placement and Routing Optimization Framework Beyond Standard Cells
#16 Multi-Level Interconnect Planning for Signal-Power-Thermal Integrity in 2.5D/3D Integration
#18 Technology-Aware 3D Placement with ILP-Based Region Planning for Soft Modules
#23 An Improved Ion-Shuttling Approach for QCCD Architectures
#27 Timing-Aware End-to-End Circuit Compilation Framework for Modular Quantum Systems
#43 Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware Reservation
#44 Gradient-Guided RC Weighting for Timing-Driven Global Routing
#46 Photonics-Aware Planning-Guided Automated Electrical Routing for Large-Scale Active Photonic Integrated Circuits
#51 IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs
#52 GrandPlan: Differentiable, Simultaneous Top-Level Floorplanning and Partition-Level Cell Placement for Large-Scale IP-Cores