Professor Chung-Kuan Cheng

BIOGRAPHY

Chung-Kuan Cheng received the B.S. and M.S. degrees in Electrical Engineering from National Taiwan University, and the Ph.D. degree in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1984.

Since 1986, he has been with the University of California, San Diego, where he was a Distinguished Professor in Computer Science and Engineering Department and an Adjunct Professor in the Electrical and Computer Engineering Department; he is currently a Professor of the Graduate Division. From 1984 to 1986, he was a senior CAD engineer at Advanced Micro Devices Inc. He served as a principal engineer at Mentor Graphics in 1999.

He has been recognized with the NCR Excellence in Teaching Award, UC San Diego School of Engineering, 1991; Distinguished Faculty Award, UC San Diego, 2013; IBM Faculty Awards, 2004, 2006, and 2007; Cadence Academic Collaboration Award, 2016; IEEE Fellow, 2000. He is a recipient of the IEEE Trans. on Computer-Aided Design Best Paper Awards, 1997 and 2002, and the ACM/IEEE ASPDAC Best Paper Award, 2022.

For physical design, his classic works include ratio cut, coined by his team to balance partitioning using rational objective functions; ancestor tree, cited in the textbook Network Flows by Ahuja, Magnanti, and Orlin; and floorplanning representation, cited in the Art of Computer Programming, Volume 4B, by Knuth. His Erdos Number is 2.

The impact of his VLSI layout research includes the O-tree for floorplan representation, which along with its extension (B* tree) has led to the leading block floorplanning method in terms of computational complexity and quality of the results; the ePlace/RePlAce placement method, which has been extended for GPU acceleration, parameter tuning via machine learning, and 3D/mixed mode placement for block-level design automation; multicommodity flow-based global routing, which ensures an error bound for VLSI global routing; and standard-cell library generation which integrates logic synthesis, topology enumeration, placement, and routing at transistor level for design- and system-technology co-optimization. His 50 Ph.D. graduates have further shaped the field through their careers in industry and academia.

Link to his Homepage