A printable version (PDF) of the technical program can be downloaded here.
Hover the mouse cursor over an entry to bring up it's abstract!
5:30 pm - 7:00 pm: Reception
7:45 am - 8:45 am: Simple Breakfast
8:45 am - 10:00 am: Welcome and Keynote Address
General Chair Message: Chris Chu (Iowa State University)
Keynote: "Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design," Anthony Hill (Texas Instruments Inc., invited) [Slides]
10:00 am - 10:30 am: Morning Break
10:30 am - 12:00 pm Session 1: Finding the Golden Tree in the Forest!
Session Chair: Gary Yeap (Synopsys Inc.)
"Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics," Andrew B. Kahng, Christopher Moyes, Sriram Venkatesh, and Lutong Wang [Slides]
"Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees," Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, and Sriram Venkatesh (Best Paper Award Nominee) [Slides]
"Construction of All Rectilinear Steiner Minimum Tree on the Hanan Grid," Sheng-En David Lin and Dae Hyun Kim [Slides]
12:00 pm - 1:30 pm: Lunch
1:30 pm - 3:30 pm Session 2: FPGA Special Session
Session Chair: Sabya Das (Xilinx Inc.)
"Challenges in Large FPGA based Logic Emulation Systems," William N. Hung (Synopsys Inc., invited)
"Flexibility: FPGAs and CAD in Deep Learning Accelerations," Gordon Chiu (Intel Corp., invited)
"Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications," Elliott Delaye and Ashish Sirasao (Xilinx Inc., invited) [Slides]
"Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework," Jason H. Anderson (University of Toronto, invited)
3:30 pm - 4:00 pm: Afternoon Break
4:00 pm - 5:30 pm Session 3: Design Flow and Power Grid Optimization
Session Chair: Mahesh Iyer (Intel Corp.)
"Concurrent High Performance Processor Design: From Logic to PD in Parallel," Leon Stok (IBM Corp., invited) [Slides]
"Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution," Andre Inacio Reis (Universidade Federal do Rio Grande do Sul, invited) [Slides]
"Power Grid Reduction by Sparse Convex Optimization," Wei Ye, Meng Li, Kai Zhong, Bei Yu, and David Z. Pan [Slides]
6:00 pm - 8:00 pm: Dinner Banquet
8:00 am - 9:00 am: Simple Breakfast
9:00 am - 10:00 am: Tuesday Keynote Address
Session Chair: David Pan (University of Texas at Austin)
Keynote: "Silicon Compilers - Version 2.0," Andreas Olofsson (DARPA, invited) [Slides]
10:00 am - 10:30 am: Morning Break
10:30 am - 12:30 pm Session 4: Statistical and Machine Learning-Based CAD
Session Chair: Ivan Kissiov (Mentor Graphics, a Siemens Business)
"Machine Learning Applications in Physical Design: Recent Results and Directions," Andrew Kahng (UC San Diego, invited) [Slides]
"Machine Learning for Feature-Based Analytics," Li-C. Wang (UC Santa Barbara, invited) [Slides]
"Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning," Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, and David Z. Pan [Slides]
12:30 pm - 2:00 pm: Lunch
2:00 pm - 3:30 pm Session 5: Three Shades of Placement!
Session Chair: Joseph Shinnerl (Mentor, a Siemens Business)
"Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs," Bon Woong Ku, Kyungwook Chang, and Sung Kyu Lim (Best Paper Award Nominee) [Slides]
"Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting," Biying Xu, Bulent Basaran, Ming Su, and David Z. Pan [Slides]
"Pin Assignment Optimization for Multi-2.5D FPGA-based Systems," Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, and Yoon Kah Leow (Best Paper Award Nominee) [Slides]
3:30 pm - 4:00 pm: Afternoon Break
4:00 pm - 5:30 pm Session 6: Commemoration for Professor Te Chiang Hu
Session Chair: Andrew B. Kahng (UC San Diego)
"Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout," Andrew B. Kahng (UC San Diego, invited) [Slides]
"Tree Structures and Algorithms for Physical Design," Chung-Kuan Cheng (UC San Diego, invited) [Slides]
"Pioneer Research on Mathematical Models and Methods for Physical Design," Chris Chu (Iowa State University, invited) [Slides]
"Theory and Algorithms of Physical Design," Te Chiang Hu (UC San Diego, invited) [Slides]
6:00 pm - 8:30 pm: Dinner Banquet
7:30 am - 8:30 am: Simple Breakfast
8:30 am - 10:30 am Session 7: Interconnect Optimization and Detailed Routing Contest Results
Session Chair: Jackey Yan (Cadence Design Systems Corp.)
"Interconnect Optimization Considering Multiple Critical Paths," Jiang Hu, Ying Zhou, Yaoguang Wei, Steve Quay, Lakshmi Reddy, Gustavo Tellez, and Gi-Joon Nam [Slides]
"Interconnect Physical Optimization," Charlie Janac (Arteris Inc., invited) [Slides]
"ISPD 2018 Initial Detailed Routing Contest and Benchmarks," Wen-Hao Liu (Cadence Design Systems Inc., invited) [Slides]
10:30 am - 10:45 am: Morning Break
10:45 am - 12:15 pm Session 8: How to Make Your Foundry Happier?
Session Chair: Jiang Hu (Texas A&M University)
"The Pressing Need for Electromigration-Aware Physical Design," Jens Lienig (Dresden University, invited) [Slides]
"On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques," Alexey Lvov, Gustavo Tellez, and Gi-Joon Nam [Slides]
"Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits," Raphael Viera, Philippe Maurine, Jean-Max Dutertre, and Rodrigo Possamai Bastos [Slides]
12:15 pm - 12:25 pm: Closing Remarks
12:25 pm - 1:30 pm: Lunch
2:00 pm - 5:00 pm: Guided tour to the Point Lobos State Natural Reserve (Location, Tour information)