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2015 International Symposium on Physical Design With a Tribute to Dr. Kurt Antreich Monterey, California, March 29-April 1, 2015 Sponsored by ACM/SIGDA with Technical
Co-Sponsorship from IEEE CAS
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PROGRAM The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI, biological or other advanced technology systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing. Regular presentations are 30 minutes.
SUNDAY, March 29 5:30 – 7:00 pm: Reception (at Vista Del Mar)
MONDAY, March 30 7:15 – 8:45 am: Breakfast (at Presidio) 8:45 – 10:00 am: Welcome and Keynote Address Host: Azadeh Davoodi (UW-Madison) [slides]
Monday Keynote: “3D VLSI: A Scalable Integration Beyond 2D”, Karim Arabi (Qualcomm) [slides]
10:00 – 10:30 am: Morning Break
10:30 am - 12:30 pm Session 1: Advanced Placement and Analog Design Session Chair: Jackey Yan (Cadence)
“A Self-Stabilizing Placement Framework”, Philipp Ochsendorf, Nils Hoppmann, Anna Hermann and Ulrich Brenner [slides]
“Coarse-grained Structural Placement for a Synthesized Parallel Multiplier”, Sungmin Bae [slides]
“Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment”, Po-Hsun Wu, Mark Po-Hung Lin, Xin Li and Tsung-Yi Ho [slides]
(Invited) “Automation of Analog IC Layout -- Challenges and Solutions”, Juergen Scheible and Jens Lienig
12:30 – 2:00 pm: Lunch (at Presidio)
2:00 – 3:30 pm Session 2: Learning Physical Design Session Chair: Hung-Ming Chen (NCTU)
“Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation”, Yu-Guang Chen, Wan-Yu Wen, Tao Wang, Yiyu Shi and Shih-Chieh Chang (best paper candidate) [slides]
“SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips”, Qin Wang, Weiran He, Hailong Yao, Tsung-Yi Ho and Yici Cai [slides]
(Invited) “Machine Learning in Simulation-based Analysis”, Li-C. Wang and Malgorzata Marek-Sadowska [slides]
3:30 – 4:00 pm: Afternoon Break
4:00 – 5:30 pm Session 3: DFM Session Chair: Hongbo Zhang (Synopsys)
(Invited) “Physical Layout Design of Directed Self-assembly Guiding Alphabet for IC Contact Hole/via Patterning”, H.-S. Philip Wong, He Yi, Maryann Tung, Kye Okabe [slides]
“A Cell-Based
Row-Structure Layout Decomposer for Triple Patterning Lithography”, Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen and Ting-Chi Wang (best paper winner) [slides]
6:00 – 8:00 pm: Dinner Banquet (at Presidio) Host: Noel Menezes (Intel)
(Invited) “Concept & Research to Revenue: An Entrepreneurial Story” by Dean Drako (IC Manage).
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TUESDAY, March 31 7:30 – 9:00 am: Breakfast (at Presidio) 9:00 – 10:00 am: Tuesday Keynote Address Host: Patrick Groeneveld (Synopsys)
Tuesday Keynote: “Analog Circuit and Layout Synthesis Revisited”, Rob Rutenbar (UIUC) [slides]
10:00 – 10:30 am: Morning Break
10:30 am – 12:00 pm Session 4: Clocking and Power Session Chair: Aiqun Cao (Synopsys)
“A Useful Skew Tree Framework for Inserting Large Safety Margins”, Rickard Ewetz and Cheng-Kok Koh [slides]
“Analytical
Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging”,
Chang Xu, Peixin Li, Guojie Luo, Yiyu Shi and Iris Hui-Ru Jiang [slides] (Invited) “Physical Design Challenges in the Chip Power Distribution Network”, Farid Najm (U of Toronto) [slides]
12:00 – 1:30 pm: Lunch (at Presidio)
1:30 – 3:30pm Session 5: Physical Design and Beyond Session Chair: Dwight Hill (Synopsys)
“Accelerated Path-Based Timing Analysis with MapReduce”, Tsung-Wei Huang and Martin D. F. Wong [slides]
“Blech Effect in Interconnects: Applications and Design
Guidelines”, Ali Abbasinasab and Malgorzata
Marek-Sadowska
[slides]
(Invited) “From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges”, Olivier Billoint (LETI) [slides]
3:30 – 4:00 pm: Afternoon Break
4:00 – 5:45 pm Session 6: Commemoration for Prof. Kurt Antreich Session Chair: Andrew Kahng (UCSD)
(Invited) “The Early Days of Circuit Placement”, Martin D.F. Wong (UIUC) [slides]
(Invited) “Force-Directed Placement of VLSI Circuits”, Hans Eisenmann (PDF Solutions GmbH) [slides] [video1] [video2]
(Invited) “Beyond GORDIAN and KRAFTWERK: EDA Research at TUM”, Ulf Schlichtmann (Technische Universität München) [slides]
6:00 – 8:00 pm: Dinner Banquet (at Presidio)
WEDNESDAY, April 1 7:00 – 8:30 am: Breakfast (at Presidio) 8:30 – 10:00 am Session 7: Placement and Contest Session Chair: Yuyen Mo (Oracle)
“Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression”, Chrystian Guth, Vinicius Livramento, Renan Netto, Renan Fonseca, José Luís Güntzel and Luiz Santos (best paper candidate) [slides]
“Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability”, Chun Kai Wang, Chuan Chia Huang, Shih Ying Liu, Ching Yu Chin, Sheng Te Hu, Wei Chen Wu and Hung Ming Chen [slides]
(Invited) “ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement”, Ismail S. Bustany, David Chinnery, Joseph R. Shinnerl and Vladimir Yutsis (Mentor Graphics) [slides]
10:00 – 10:30 am: Morning Break
10:30 am – 12:00 pm Session 8: FreePDK Session Chair: David Chinnery (Mentor Graphics)
(Invited) “FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology”, Kirti Bhanushali and Rhett Davis [slides]
(Invited) “Open Cell Library in 15nm FreePDK Technology”, Mayler Martins, Jody Matos, Renato Ribas, Andre Reis, Guilherme Schlinker, Lucio Rech and Jens Michelsen [slides]
(Invited) “Design Rule Management and its Applications in 15nm FreePDK Technology”, Michiel Oostindie, Maarten Berkens and Coby Zelnik [slides]
(Invited) “A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design”, Jody Matos, Augusto Neutzling, Renato Ribas and Andre Reis [slides]
12:00 – 12:10 pm: Closing Remarks
12:10 – 1:30 pm: Lunch (at Presidio)
There will be social activities in the afternoon of April 1, 2015. |