2012
International
Symposium
on
Physical
Design
With a Tribute to Professor C.-
Napa Valley,
California,
March
25-28,
2012
www.ispd.cc
Sponsored by ACM/SIGDA with Technical
Co-Sponsorship from IEEE CAS
Additional support from ATopTech, Cadence, IBM Research,
Institute of Information and Computing Machinery, Industrial Technology Research Institute,
Intel Corporation, Mentor Graphics, National Taiwan University,
Oracle,
SpringSoft, Synopsys,
and TSMC
|
PROGRAM The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI and biological systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing.
Regular presentations are 30 minutes. Short presentations (S) are 15 minutes.
SUNDAY,
March 25
5:30 - 7:00 pm: Evening Reception
MONDAY,
March 26
8:30 - 9:45
am:
Welcome and Keynote Address
Host:
Jiang Hu
(Texas A&M University)
Keynote Talk:
Lithography Till the End of Moore's Law
9:45
-
10:15 am:
Morning
Break
10:15 am - 12:15 pm Session 1: Advanced Processes
Chair:
Markus Olbrich
(University
of Hannover)
(Invited talk) Design-Aware Lithography
Graph-Based Subfield
Scheduling for Electron-Beam Photomask Fabrication
(Best Paper Nominee)
A Polynomial Time Exact
Algorithm for Self-Aligned Double Patterning Layout Decomposition
Flexible Self-aligned
Double Patterning Aware Detailed Routing with Prescribed Layout Planning
12:15
-
1:45 pm:
Lunch
1:45
-
3:15
pm Session 2:
Emerging Challenges
and Technologies
Chair:
David
Pan
(UT-Austin)
(Invited
talk)
Integration, Architecture, and
Applications of 3D CMOS-Memristor Circuits
A Fast Estimation of SRAM Failure Rate Using Probability Collectives
Fang Gong, Sina Basir-Kazeruni, Lara Dolecek and Lei He
[slides]
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic
Biochips
3:15
-
3:45
pm:
Afternoon
Break
3:45
-
5:45
pm
Session
3:
Commemoration for Professor C.-L. Liu
(Invited talk) Transformation from Ad Hoc EDA to Algorithmic EDA
(Invited talk) On
Simulated Annealing in EDA
(Invited talk) On Pioneering Nanometer-Era Routing Problems
(Invited talk) I attended the Nineteenth Design Automation Conference
5:45 - 6:15 pm: Reception 6:15 - 8:45 pm: Dinner Banquet Honoring Prof. C.-L. Liu: Everybody Loves Dave
TUESDAY, March 27
8:30
-
10:00
am Session 4: Analog, Datapath, and
Detailed Placement
Routability-driven
Placement Algorithm for Analog Integrated Circuits
Keep it Straight:
Teaching Placement how to Better Handle Designs with Datapaths
(Best Paper Nominee)
10:00
-
10:30
am:
Morning
Break
|
10:30
am
-
12:15
pm Session 5:
Power and Thermal Modeling and Optimization
(Invited talk) Power-Grid (PG) Analysis
Challenges
for Large Microprocessor Designs (Our Experience with Oracle Sparc
Processor Designs)
Efficient On-line
Module-Level Wake-Up Scheduling for High Performance Multi-Module
Designs
Chung-Kuan Cheng,
Peng Du, Andrew Kahng and Shih-Hung Weng
(S) TSV-Constrained
Micro-Channel Infrastructure Design for Cooling Stacked 3D-ICs
12:15
- 1:45 pm: Lunch Break
1:45
- 3:45
pm
Session 6: Clocking and
Routing
Chair:
Yiyu Shi
(Missouri
University of Science and Technology)
(Invited talk) Construction of
Minimal
Functional
Skew
Clock-trees
Novel Pulsed-Latch
Replacement Based on Time Borrowing and Spiral Clustering
On Constructing Low
Power and Robust Clock Tree via Slew Budgeting
3:45
- 4:15
pm: Afternoon Break
4:15 - 5:45 pm Session 7: Gate Sizing
Simultaneous Clock
and Data Gate Sizing Algorithm with Common Global Objective
Construction of
Realistic Gate Sizing Benchmarks With Known Optimal Solutions
(Invited
talk)
The ISPD-2012 Discrete Cell Sizing Contest and Benchmark Suite
WEDNESDAY, March 28
8:30 - 10:00
am Session 8:
Congestion-Driven Logic and Physical Synthesis
(Invited
talk)
Towards Layout-Friendly
High-Level Synthesis
(Invited
talk)
Synthesis for Advanced Nodes
(Invited
talk)
Reality-Driven
Physical Synthesis
10:00
-
10:30
am: Morning
Break
10:30
am
-
12:00
pm Session 9: Floorplanning and Mixed-Size Placement
Chair:
Ting-Chi Wang
(National Tsing Hua University)
Optimal Slack-Driven
Block Shaping Algorithm in Fixed-Outline Floorplanning
(Best Paper Nominee)
(S) Scalable
Hierarchical Floorplanning for Fast Physical Prototyping of
Systems-on-Chip
MAPLE: Multilevel
Adaptive PLacEment for Mixed-Size Designs
(Best Paper Nominee)
12:00
-
12:10 pm: Closing Remarks
2:00 - 3:30 pm: Winery Tour and Wine Tasting |