2011 International Symposium on Physical Design With Commemoration for Professor Ernest KuhHotel Mar Monte, Santa Barbara, California March 27-30, 2011 www.ispd.ccSponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS Additional support from ATopTech, Cadence, First International Computer, IBM Research, Intel Corporation, Mentor Graphics, National Taiwan University, SpringSoft, Synopsys, Taiwan Intelligent Electronics Consortium, TSMC and VeriSilicon PROGRAM: The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI and biological systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing. The ISPD'11 Best Paper Award nominees are marked with an asterisk (*). |
SUNDAY, March 275:30 - 7:00 pm: Evening Reception MONDAY, March 288:30 - 9:45 am: Welcome and Keynote Address Host: Yao-Wen Chang (National Taiwan University) Keynote Talk: Robust Design of Power-Efficient VLSI Circuits Massoud Pedram (University of Southern California) |slides | 9:45 - 10:15 am: Morning Break 10:15 am - 12:00 pm Session 1: Commemoration for Professor Ernest Kuh Chair: Prashant Saxena (Synopsys) Invited talk Ernest Kuh (University of California at Berkeley) (Invited talk) Placement and Beyond in Honor of Ernest S. Kuh C.-K. Cheng (University of California at San Diego) |slides | (Invited talk) From Academic Ideas to Practical Physical Design Tools Ren-Song Tsay (National Tsing-Hua University) |slides | (Invited talk) On Old and New Routing Problems Malgorzata Marek-Sadowska (University of California at Santa Barbara) |slides | 12:00 - 1:30 pm: Lunch 1:30 - 3:00 pm Session 2: Clock Network Synthesis and Routing Chair: Igor Markov (University of Michigan) *Grid-to-Ports Clock Routing for High Performance Microprocessor Designs Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young and C. N. Sze |slides | *Cross Link Insertion for Improving Tolerance to Variations in Clock Network Synthesis Tarun Mittal and Cheng-Kok Koh |slides | Synthesis of Low Power Clock Trees for Handling Power-supply Variations Shashank Bujimalla and Cheng-Kok Koh |slides | 3:00 - 3:30 pm: Afternoon Break 3:30 - 5:30 pm Session 3: Routing Chair: Jens Lienig (Dresden University of Technology) RegularRoute: An Efficient Detailed Router with Regular Routing Patterns Yanheng Zhang and Chris Chu |slides | An Enhanced Global Router with Consideration of General Layer Directives Tsung-Hsien Lee, Yen-Jung Chang and Ting-Chi Wang |slides | Obstacle-Aware Length-Matching Bus Routing Jin-Tai Yan and Zhi-Wei Chen |slides | Co-optimization of Droplet Routing and Pin Assignment in Disposable Digital Microfluidic Biochips Yang Zhao and Krishnendu Chakrabarty 6:00 - 8:30 pm: Dinner Banquet Dinner Session: Professor Kuh and I
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TUESDAY, March 298:30 - 10:00 am Session 4: Physical Design for 3D ICs Chair: Azadeh Davoodi (University of Wisconsin) (Invited talk) 3D ICs for Tera-Scale Computing - a Case Study Tanay Karnik, Dinesh Somasekhar and Shekhar Borkar (Intel) (Invited talk) Advances in 3D Integrated Circuits Bob Patti (Tezzaron) Assembling 2D Blocks into 3D Chips Johann Knechtel, Igor L. Markov and Jens Lienig 10:00 - 10:30 am: Morning Break 10:30 am - 12:00 pm Session 5: Placement and Floorplanning Chair: Inki Hong (Cadence) (Invited talk) Automated Placement for Custom Digital Designs Tung-Chieh Chen (SpringSoft) |slides | Quantifying Academic Placer Performance on Custom Designs Samuel I. Ward, David A. Papa, Zhuo Li, C. N. Sze, Charles J. Alpert and Earl Swartzlander |slides | Regularity-Constrained Floorplanning for Multi-Core Processors Xi Chen, Jiang Hu and Ning Xu |slides | 12:00 - 1:30 pm: Lunch 1:30 - 3:30 pm Session 6: Register Clustering and Placement Chair: Salim Chowdhury (Oracle) Power-Driven Flip-Flop Merging and Relocation Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo and Wai-Kei Mak |slides | INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval Graphs Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Evan Yu-Wen Tsai and Lancer Sheng-Fong Chen |slides | *Obstacle-aware Clock-tree Shaping during Placement Dong-Jin Lee and Igor L. Markov |slides | Timing Slack Aware Incremental Register Placement with Non-uniform Grid Generation for Clock Mesh Synthesis Jianchao Lu, Xiaomi Mao and Baris Taskin |slides | 3:30 - 4:00 pm: Afternoon Break 4:00 - 5:30 pm Session 7: DFM Routing and Routability-Driven Placement Contest Chair: Natarajan Viswanathan (IBM) (Invited talk) Impact of Manufacturing on Routing Methodology at 32/22 nm Alex Volkov (Mentor Graphics) |slides | (Invited talk) The ISPD-2011 Routability-Driven Placement Contest and Benchmark Suite Natarajan Viswanathan, Charles J. Alpert, C. N. Sze, Zhuo Li, Gi-Joon Nam and Jarrod A. Roy |slides | 6:30 - 8:30 pm: Dinner Banquet at China Pavilion(map) WEDNESDAY, March 308:30 - 10:00 am Session 8: Design for Manufacturing Chair: Martin Wong (University of Illinois) (Invited talk) Vertical Slit Transistor Based Integrated Circuits (VeSTICs): Feasibility Study Wojciech Maly (Carnegie Mellon University) (Invited talk) Litho and Design: Moore Close Than Ever Vivek Singh (Intel) |slides | *E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters Kun Yuan and David Z. Pan |slides | 10:00 - 10:30 am: Morning Break 10:30 am - 12:00 pm Session 9: Circuit Optimization and Modeling Chair: Yiyu Shi (Missouri University of Science and Technology) A Realistic Power Grid Verification Based on Hierarchical Current/Power Constraints Chung-Kuan Cheng, Peng Du, Andrew Kahng, Grantham K. H. Pang, Yuanzhe Wang and Ngai Wong |slides | Lagrangian Relaxation for Gate Implementation Selection Yi-Le Huang, Jiang Hu and Weiping Shi |slides | Stochastic Analog Circuit Behavior Modeling by Point Estimation Method Fang Gong, Hao Yu and Lei He |slides | 12:00 - 12:10 pm: Closing Remarks 12:10 - 1:40 pm: Lunch 2:00 - 6:00 pm: Tour Solvang, a Danish town; flower fields at Lompoc
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