2009 International Symposium on Physical Design Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE/CAS and IEEE/CEDA |
PROGRAM Regular paper presentations run 25 minutes. Invited talks are 30 minutes. The ISPD'09 Best Paper Award nominees are marked with an asterisk (*). SUNDAY, MARCH 29 5:30 - 7:00 pm Evening Reception MONDAY, MARCH 30 8:30 - 9:30 am Welcome and Keynote Address (Keynote Talk) One Look into the Future of CMOS Chip Design 9:30 - 10:00 am Morning Break 10:00 - 11:45 am Session 1: Global Layout Planning (Invited Talk) Early Stage Analysis for Power Distribution Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs Multi-voltage Floorplan Design with Optimal Voltage Assignment Robust Interconnect Communication Capacity Algorithm by Geometric Programming 11:45 am - 1:30 pm Lunch 1:30 - 3:10 pm Session 2: Physical Synthesis and Circuit Optimization * A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion Fast Buffering for Optimizing Worst Slack and Resource Consumption in Repeater Trees On Improving Optimization Effectiveness in Interconnect-Driven Physical Synthesis 3:10 - 3:40 pm Afternoon Break 3:40 - 5:40 pm Session 3: Nanotechnology: CMOS and Beyond (Invited Talk) Will 22nm Be Our Catch-22? Design and CAD Challenges (Invited Talk) Vertical Slit Transistor-based Integrated Circuits (VeSTICs) Paradigm |
TUESDAY, MARCH 31 8:30 - 10:10 am Session 4: Analog Design: Tools and Methodologies (Invited Talk) Accelerated Design of Analog, Mixed-Signal Circuits with Titan (Invited Talk) Physical Design Methodology for Analog Circuits in a System-on-a-Chip Environment (Invited Talk) Constraint-driven Design - The Next Step Towards Analog Design Automation 10:10 - 10:40 am Morning Break 10:40 - 12:00 pm: Session 5: Layout Optimization for FPGAs and Regular Fabrics * Transistor-Level Layout of High-Density Regular Circuits Physical Optimization for FPGAs Using Post-Placement Topology Rewriting A Routing Approach to Reduce Glitches in Low Power FPGAs 12:00 - 1:30 pm Lunch 1:30 - 3:10 pm Session 6: Manufacturability and Yield Enhancement Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization An Automatic Optical-Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization Redundant Via Insertion with Wire Bending Wire Shaping Is Practical 3:10-3:40 pm Afternoon Break 3:40-5:05 pm Session 7: Clocking and the ISPD'09 Clock Network Synthesis Contest (Invited Talk) Industrial Clock Synthesis An Algorithm for Routing with Capacitance/Distance Constraints for Clock Distribution in Microprocessors (Invited Talk) ISPD'09 Clock Network Synthesis Contest Results WEDNESDAY, APRIL 1 8:30 - 10:10 am Session 8: Advances in Routing Critical-Trunk-based Obstacle-Avoiding Rectilinear Steiner Tree Routing for Delay and Slack Optimization Layer Assignment for Via Optimization in Multi-layer Global Routing A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment Diffusion-Driven Congestion Reduction for Substrate Topological Routing 10:10am - 10:40am Morning Break 10:40 - 12:00 pm Session 9: Post-Si Prediction and Debug (Invited Talk) The Challenges of Correlating Silicon and Models in High Variability CMOS Process * Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations 12:00 - 12:15 pm Closing Remarks |