2008 International Symposium on Physical Design Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS |
PROGRAM Regular paper presentations run 25 minutes. Invited talks are 30 minutes. SUNDAY, APRIL 13 5:30 - 7:00 pm Evening Reception MONDAY, APRIL 14 8:30 - 9:30 am Welcome and Keynote Address (Keynote Talk) Design or Manufacturing: Which will be the best driver for the future of the semiconductor roadmap? 9:30 - 10:00 am Morning break 10:00 - 11:40 am Session 1: Physical Optimization Techniques with Buffering and Gate Sizing RUMBLE: An Incremental Timing-driven Physical Synthesis Optimization Algorithm Robust Gate Sizing via Mean-Excess Delay minimization Multi-Scenario Buffer Insertion in Multi-core Processor Designs Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree Construction 12:00 - 1:30 pm Lunch 1:30 - 3:10 pm Session 2: Advances in Placement Metal-Density Driven Placement for CMP Variation and Routability Highly Efficient Gradient Computation for Density Constrained Analytical Placement Problems Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement 3-D Floorplanning Using Labeled Tree and Dual Sequences 3:10 - 3:40 pm Afternoon break 3:40 - 5:20 am Session 3: Statistical and Physical Design for Manufacturability - Act II (Invited talk) Variations, Margins, and Statistics (Invited talks) How To Get Real MAD 6:30 - 9:30 pm: Dinner Banquet TUESDAY, APRIL 15 8:30 - 10:10 am Session 4: Interconnect Synthesis and Structured ASIC (Invited talk) Fast Interconnect Synthesis with Layer Assignment (Invited talk) RF Interconnects for Communications On-Chip (Invited Talk) Placement Challenges for Structured ASICs 10:10 - 10:40 pm Morning break 10:40 - 12:00 pm: Session 5: Logic Optimizations for Physical Synthesis A Framework for Layout-level Logic Restructuring |
Optimizing Non-Monotonic Interconnect Using Functional Simulation and Logic Restructuring Reap What You Sow: Spare Cells for Post-Silicon Metal Fix 12:00 - 1:30 pm Lunch 1:30 - 3:10 pm Session 6: Advances in Routing Optimal Post-Routing Redundant Via Insertion Efficient Multilayer Routing Based on Obstacle-Avoiding Preferred Direction Steiner Tree An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment for a Gridless Routing System with Fast Pseudo-Tile Extraction 3:10-3:40 pm Afternoon break 3:40-5:10 pm Session 7: Modern Global Routing Issues and ISPD'08 Global Routing Contest (Invited Talk) Issues in Global Routing The Coming of Age of (Academic) Global Routing ISPD'08 Global Routing Contest Results 6:30 - 9:30 pm: Dinner Banquet WEDNESDAY, APRIL 16 8:30 - 10:10 am Session 8: Electrical Issues and Clock Network Design in Physical Synthesis Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise Stress Aware Layout Optimization Discrete Buffer and Wire Sizing for Linked-based Non-tree Clock Networks Activity and Register Placement Aware Gated Clock Network Design 10:10am - 10:40am Morning Break 10:40 - 12:00 pm Session 9: Physical Design for Bio-Microfluidics (Invited Talk) Automated Design of Digital Microfluidic Lab-on-Chip under Pin-Count Constraints (Invited Talk) Physical Design Issues in Biofluidic Microchips A High-Performance Droplet Router for Digital Microfluidic Biochips 12:00 - 1:00 pm Closing Remarks & Lunch SYMPOSIUM REGISTRATION Please register on-line at http://www.ispd.cc by March 12th, 2008 for the early registration discount rates.
HOTEL ACCOMODATIONS AND TRAVEL ISPD will be held at the Embassy Suites Portland Downtown Hotel, in Portland, Oregon. The hotel is located in the downtown area near the Oregon Convention Center.Embassy Suites Portland Downtown |