ISPD 2007
March 18 - 21, 2007
Dolce Lakeway Resort and Spa, Austin (Texas), USA
Technical Program (.doc, .pdf)
The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance analysis and verification.
Regular paper presentations run 25 minutes. Invited talks are 30-35 minutes.
SUNDAY, MARCH 18
5:30 7:00 pm Evening Reception
MONDAY, MARCH 19
8:30 9:30 am Welcome and Keynote Address (ppt)
Host: Patrick Madden/SUNY Binghamton
(Keynote) Cell Architecture Key Physical Design Features and Methodology
Jim Khale, IBM
9:30 9:55 am Morning break
9:55 - 12:05 am Session 1: Multicore and DFM
Chair: Hidetoshi Onodera, Kyoto U
(Invited talk) An 8-core, 64-thread, 64-bit Power Efficient SPARC SoC (Niagara2) (pdf)
Tim Johnson and Umesh Nawathe, Sun Microsystems
Dummy Fill Density Analysis with Coupling Constraints (ppt)
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan (Kevin) Chao and Martin D.F. Wong
Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation (ppt)
Vishal Khandelwal and Ankur Srivastava
Is Your Layout Density Verification Exact ? --- A Fast Exact Algorithm For Density Calculation (ppt)
Hua Xiang, Kai-Yuan (Kevin) Chao, Ruchir Puri and Martin D.F. Wong
Pattern Sensitive Placement For Manufacturability (ppt)
Shiyan Hu and Jiang Hu
12:05 1:25 pm Lunch
1:25 3:30 pm: Session 2: Circuit Analysis & Optimization
Chair: Rajendran Panda (Freescale)
Worst-case delay analysis considering the variability of transistors and interconnects (ppt)
Takayuki Fukuoka, Akira Tsuchiya and Hidetoshi Onodera
Accurate Power Grid Analysis with Behavioral Transistor Network Modeling (ppt)
Anand Ramalingam, Giri Venkata Devarayanadurg and David Z. Pan.
EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method for Physical Optimization (ppt)
Yiyu Shi and Lei He
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off (ppt)
Salim Chowdhury and John Lillis
Circuit Optimization for Leakage Power Reduction using Multi-Threshold Voltages for High Performance Microprocessors (ppt)
Jeegar Shah, Marius Evers, Jeff Trull and Alper Halbutogullari
3:30 4:00 pm Afternoon break
4:00 5:30 pm: Session 3: Panel on Rules vs Tools Whats the right way to address IC manufacturing complexity?
Moderator: Lou Scheffer, Cadence (ppt)
Panelists: Lars Liebmann (IBM)
Riko Rakojcic (Qualcomm) (ppt)
David White (Cadence) (ppt)
6:30 9:30 pm: Dinner Banquet
TUESDAY, MARCH 20
8:30 9:30am Session 4: Future Interconnects
Chair: Yao-Wen Chang, National Taiwan Univ.
(Invited talk) Carbon Nanotube Interconnects (pdf)
Azad Naeemi and James D. Meindl, Georgia Institute of Technology
(Invited talk) Optical Interconnects: A Viable Solution for Interconnection Beyond 10 Gbit/sec (pdf)
Ray Chen, Univ. of Texas at Austin
9:30 10:00 pm Morning break
10:00 12:05 pm Session 5: Placement
Chair: Chris Chu, Iowa State U
X-Architecture Placement Based on Effective Wire Models (ppt)
Tung-Chieh Chen, Yi-Lin Chuang and Yao-Wen Chang
A Morphing Approach to Address Placement Stability (ppt)
Philip Chong and Christian Szegedy
Mixed-Size Placement with Fixed Macrocells using Grid-Warping (ppt)
Zhong Xiu and Rob Rutenbar
An Effective Clustering Algorithm for Mixed-size Placement (ppt)
Jianhua Li and Laleh Behjat
A Stable Fixed-Outline Floorplanning Method (ppt)
Song Chen and Takeshi Yoshimura
12:05 1:25 pm Lunch
1:25 3:30 pm Session 6: Routing
Chair: Jens Lienig, TU Dresden
Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction (ppt)
Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang and Chia-Lin Yang
Maze Routing Steiner Trees with Effective Critical Sink Optimization (ppt)
Renato Hentschke, Jagannathan Narasimhan, Marcelo Johann and Ricardo Reis
Semi-Detailed Bus Routing with Variation Reduction (ppt)
Fan Mo and Robert Brayton
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space (ppt)
Keith So
Algorithms for Automatic Length Compensation of Busses (ppt)
Matthew A. Smith, Lars Anton Schreiner, Erich Barke and Volker Meyer zu Bexten
3:30-4:00pm Afternoon break
4:00-5:30 pm Session 7: ISPD07 Global Routing Contest and Placement Contest Updates
Chair: Gi-Joon Nam (IBM)
ISPD07 Global Routing Contest (pdf)
Gi-Joon Nam, IBM
Updates of the ISPD Placement Contest (pdf)
Gi-Joon Nam, IBM
6:30-9:30 pm: Dinner Banquet
WEDNESDAY, MARCH 21
8:30 10:30 am Session 8: Statistical and Physical Design for Manufacturability
Chair: Prashant Saxena, Synopsys
(Invited talk) The Good, the Bad, and the Statistical
Noel Menezes, Intel (pdf)
(Invited talk) Fear, Uncertainty and Statistics (pdf)
Chandu Visweswariah, IBM
(Invited talk) Variation and Litho Driven Physical Implementation System
Shankar Krishnamoorthy, Sierra Design Automation(pdf)
(Invited talk) A DFM Aware, Space Based Router
David Cross, Eric Nequist, and Louis Scheffer, Cadence (ppt)
10:30am 11:00am Morning Break
11:0012:15pm Session 9: Clock & Interconnect
Chair: Rob Mains, Sun Microsystems
Minimal Skew Clock Embedding Considering Time Variant Temperature Variation with Automatic Correlation Extraction (ppt)
Hao Yu, Yu Hu, Chun-chen Liu and Lei He
An Efficient Clustering Algorithm for Low Power Clock Tree Synthesis (ppt)
Rupesh Shelar
A Methodology for Interconnect Dimension Determination (ppt)
Jeff Cobb, Rajesh Garg and Sunil Khatri
12:15 12:25 pm Closing Remarks