ISPD 2006 Technical Program
SUNDAY, APRIL 9
5:30 - 7:00 pm Evening Reception
MONDAY, APRIL 10
8:30 - 9:40 am Welcome and Keynote Address
Host: Lou Scheffer/Cadence
Welcome Message (Slides)
Lou Scheffer / Cadence
Commercial CAD: Challenges and Opportunities (Slides)
Ted Vucurevich / Cadence
9:40 - 10:00 am Morning break
10:00 - 12:00 am Session 1: Timing and Variability
Session Chair: Janet M. Wang (U of Arizona)
Robust Extraction of Spatial Correlation (Slides)
Jinjun Xiong, Vladimir Zolotov, Lei He
Timing Analysis in Presence of Supply Voltage and Temperature
Variations (Slides)
B. Lasbouygues, R. Wilson, N. Azemard, P. Maurine
Probabilistic Evaluation of Solutions in Variability-Driven
Optimization (Slides)
Azadeh Davoodi, Ankur Srivastava
MSMOR: Generalized Second Order Arnoldi Method for Model Order
Reduction with Multiple Non-impulse Sources (Slides)
Yiyu Shi, Hao Yu, Lei He
Non-Gaussian Statistical Parameter Modeling for SSTA with Confidence
Interval Analysis (Slides)
Lizheng Zhang, Jun Shao, Charlie Chungping Chen
12:00 - 1:20 pm Lunch
1:20 - 3:05 pm Session 2: Failure is Not An Option
Session Chair: Andrew B. Kahng (UCSD)
Introduction to Electromigration-Aware Physical Design (Invited) (Slides)
Jens Lienig / TU Dresden
IC Failure Mechanisms Yesterday, Today, Tomorrow: Implications from
Test to DFM (Invited) (Slides)
Ann Gattiker / IBM
3:05 - 3:30 pm Afternoon break
3:30 - 5:30 pm Session 3: Routing
Session Chair: Hardy K. S. Leung (Magma)
An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction
in the Lambda-Geometry Plane (Slides)
Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu and Guiying Yan
An Optimal Jumper Insertion Algorithm for Antenna Avoidance/Fixing on
General Routing Trees with Obstacles (Slides)
Bor-Yiing Su, Yao-Wen Chang, Jiang Hu
NEMO: A New Implicit Connection Graph-based Gridless Router with
Multi-Layer Planes and Pseudo-Tile Propagation (Slides)
Xin-Yu Chen, Yih-Lang Li, Zhi-Da Lin
Prediction and Reduction of Routing Congestion (Slides)
Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian
Seeing the Forest and the Trees: Steiner Wirelength Optimization in
Placement (Slide)
Jarrod A. Roy, James F. Lu and Igor L. Markov
6:30 - 9:30 pm: Dinner Banquet
TUESDAY, APRIL 11
8:30 - 10:20 am Session 4: Power and Noise
Session Chair: Charlie Chen (U of Wisconsin)
Floorplan and Power / Ground Network Co-Synthesis for Fast Design
Convergence (Slides)
Chen-Wei Liu and Yao-Wen Chang
Noise Driven In-Package Decoupling Capacitor Optimization for Power
Integrity (Slides)
Jun Chen, Lei He
Efficient Decoupling Capacitor Planning via Convex Programming Methods (Slides)
Andrew Kahng, Bao Liu, Sheldon Tan
High Accurate Pattern Based Precondition Method for Extremely Large
Power / Ground Grid Analysis (Slides)
Jin Shi, Yici Cai, Xianlong Hong, Shelton Tan
Optimal Partitioned Fault-Tolerant Bus Layout for Reducing Power in
Nanometer Designs (Slides)
Shanq-Jan Ruan, Edwin Naroska, Chun-Chih Chen
10:20 - 10:50 pm Morning break
10:50 - 12:10 am Session 5: Optimized Interconnect
Session Chair: Prashant Saxena (Synopsys)
Efficient Generation of Short and Fast Repeater Tree Topologies (Slides)
Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen
Fast Buffer Insertion Considering Process Variations (Slides)
JinJun Xiong, Lei He
Physical Design of the Brain (Invited)
Dmitri Chklovskii / Cold Spring Harbor
12:10 am - 1:40 pm Lunch
1:40 - 2:55 pm Session 6: Chip-Level Timing & Wiring
Session Chair: Patrick McGuinness (Freescale)
Integrated Retiming and Simultaneous Vdd / Vth Scaling for Total Power
Minimization (Slides)
Mongkol Ekpanyapong, Sung-Kyu Lim
Statistical Clock Tree Routing for Robustness to Process Variations (Slides)
Uday Padmanabhan, Janet M. Wang, Jiang Hu
Variation Tolerant Buffered Clock Network Synthesis with Cross Links (Slides)
Anand Rajaram, David Z. Pan
2:55 - 3:25 pm Afternoon break
3:25 - 5:30 pm Session 7: Big Designs and the ISPD06 Placement
Contest
Session Chair: Bill Halpin (Synplicity)
Chip Assembly: A New Paradigm in Heirarchical Physical Design (Invited)
(Slides)
P. V. Srinivas / Director of Engineering, Sierra Design
Physical Design Challenges for Multi-Million Gate SoCs - An
STMicroelectronics Perspective (Invited)
Francois Remond / STMicro
ISPD06 Placement Contest and Benchmark Suite (Slides)
Gi-Joon Nam / IBM
6:30 - 9:30 pm: Dinner Banquet
WEDNESDAY, APRIL 12
8:30 - 10:20 am Session 8: Industrial Clocking
Session Chair: David Pan (U of Texas)
Clock Tree Synthesis Challenges for Ultra-Low Power Designs (Slides)
Arjun Rajagopal / TI
Clockless IC Design (Slides)
Ad Peeters / Handshake Solutions
9:30 am - 10:00 am Morning break
10:00 - 11:50 am Session 9: Placement
Session Chair: Bill Swartz (InternetCAD)
Solving Hard Instances of Floorplacement (Slides)
Aaron Ng, Rajat Aggarwal, Venky Ramachandran, Igor Markov
Integrating Dynamic Thermal Via Planning with 3D Floorplanning
Algorithm (Slides)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah
Yang, Vijay Pitchumani, Chung-Kuan Cheng
Effective Linear Programming-based Placement Methods (Slides)
Sherief Reda, Amit Chowdhary
Improved Method of Module Placement with Symmetry Constraints for
Analog IC Layout Design (Slides)
Shinichi Koda, Kunihiro Fujiyoshi, Chikaaki Kodama
A Net-Reduction Based Clustering Preprocessing Algorithm (Slides)
Jianhua Li, Laleh Behjat
11:55 - 12:00 pm Closing Remarks
Placement Contest Short Papers
Satisfying Whitespace Requirements in Top-down Placement
Jarrod Roy, David Papa, Aaron Ng, Igor Markov
Dragon2006: Blockage-aware Congestion-controlling Mixed-sized Placer
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid
Sarrafzadeh
mPL6: Enhanced Multilevel Mixed-size Placement
Tony Chan, Jason Cong, Joseph Shinnerl, Kenton Sze, Min Xie
NTUPlace2: A Hybrid Placer Using Partitioning and Analytical Techniques
Zhe-Wei Jiang, Tung-Chieh Cheny, Tien-Chang Hsuy, Hsin-Chen Chenz,
Yao-Wen Chang
A Fast Implmentation of APlace
Andrew B. Kahng, Qinke Wang