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ACM International
Symposium on Physical Design
Doubletree
Hotel, Monterey, California
April 6 - 9, 2003
www.ispd.cc
Sponsored by ACM/SIGDA with Technical Cosponsorship
from IEEE CAS
Additional
support from Cadence, IBM, Intel, Magma, Numerical
Technologies, and Synopsys
FINAL
PROGRAM
The
International Symposium on Physical Design provides
a high-quality forum for the exchange of ideas and
results in critical areas related to the physical
design of VLSI systems. The scope of this symposium
includes all aspects of physical design, from interactions
with behavior- and logic-level synthesis, to back-end
performance analysis and verification. |
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Sessions:
[Keynote]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Foreword
Call for Papers - ISPD 2004
ISPD'03 Symposium Organization
Host: M. Pedram (University of Southern California)
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Physical Design: The Whole Enchilada [p. 3]
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R. Camposano (Synopsis Inc.)
Organizer: C. J. Alpert (IBM Corporation)
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Important Placement Considerations for Modem VLSI Chips [p. 6]
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P. Villarrubia (IBM Corporation), R. Vandarajan (Cadence Design Sys. Inc.)
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Convergence of Placement Technology in Physical
Synthesis: Is Placement really a point tool?
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Ravi Varadarajan (Cadence Design Systems)
Chair: M. Marek-Sadowska (University of California at Santa Barbara)
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3D Thermal-ADI ÷ An Efficient Chip-Level Transient Thermal Simulator [p. 10]
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T.-Y. Wang, Y.-M. Lee (Univ. of Wisconsin at Madison), C. C.-P. Chen (National Taiwan Univ.)
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Capturing Crosstalk-Induced Waveform for Accurate Static
Timing Analysis [p. 18]
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M. Hashimoto, Y. Yamada, H. Onodera (Kyoto University)
PowerPoint slides
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Closed Form Expressions for Extending Step Delay
and Slew Metrics to Ramp Inputs [p. 24]
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C. V. Kashyap, C. J. Alpert, F. Liu, A. Devgan (IBM Corporation)
PowerPoint slides
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Explicit Gate Delay Model for Timing Evaluation [p. 32]
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M. Shao (University of Texas at Austin), M. D. F. Wong (Univ. of Illinois at Urbana-Champaign),
H. Cao (Motorola Inc.), Y. Gao, L.-P. Yuan (Synopsis Inc.),
L.-D. Huang, S. Lee (University of Texas at Austin)
PowerPoint slides
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Signal Integrity Management in an SoC Physical Design Flow [p. 39]
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M. Becer, R. Vaidyanathan, C. Oh, R. Panda (Motorola Inc.)
PDF slides
Organizer & Chair: R. Rutenbar (Carnegie Mellon University)
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There is Life Left in ASICs [p. 48]
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L. Stok (IBM TJ Watson Research Center), J. Cohn (IBM Microelectronics)
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The Scaling Challenge: Can Correct-by-Construction Design Help? [p. 51]
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P. Saxena, N. Menezes, P. Cocchini, D. A. Kirkpatrick (Intel Labs)
PowerPoint slides
Chair: P. Madden (SUNY Binghamton)
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Timing Driven Force Directed Placement with Physical Net Constraints [p. 60]
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K. Rajagopal (Intel Corporation), T. Shaked (Intel Corporation & University of Washington),
Y. Parasuram, T. Cao, A. Chowdhary (Intel Corporation),
B. Halpin (Intel Corporation & Syracuse University)
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Fine Granularity Clustering for Large Scale Placement Problems [p. 67]
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B. Hu, M. Marek-Sadowska (University of California at Santa Barbara)
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Partition-Driven Standard Cell Thermal Placement [p. 76]
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G. Chen (Synopsis Inc.), S. Sapatnekar (University of Minnesota)
PowerPoint slides
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Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff
in Performance-Driven Bipartitioning [p. 81]
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A. B. Kahng, X. Xu (University of California at San Diego)
PowerPoint slides
Chair: A. B. Kahng (University of California at San Diego)
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Optimality, Scalability and Stability Study of Partitioning
and Placement Algorithms [p. 88]
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J. Cong, M. Romesis, M. Xie (University of California at Los Angeles)
PowerPoint slides
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Benchmarking For Large-scale Placement and Beyond [p. 95]
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S. N. Adya (University of Michigan), M. C. Yildiz (SUNY Binghamton),
I. L. Markov (University of Michigan), P. G. Villarrubia (IBM Corporation),
P. N. Parakh (Monterey Design Systems), P. H. Madden (SUNY Binghamton)
PowerPoint slides
Organizer & Chair: M. Pedram (University of Southern California)
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A Complete Design for Power Methodology and Flow for Large ASICs [p. 106]
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R. X. Nijssen, E. P. Huijbregts (Magma Design Automation)
Organizer & Chair: R. X. Nijssen (Magma Design Automation)
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Layout Impact Resolution Enhancement Techniques:
Impediment or Opportunity? [p. 110]
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L. W. Liebmann (IBM Corporation)
PDF slides
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Advanced Routing in Changing Technology Landscape [p. 118]
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H. K.-S. Leung (Magma Design Automation)
PowerPoint slides
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Research Directions for Coevolution of Rules and Routers [p. 122]
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A. B. Kahng (University of California at San Diego)
Chair: C. C.-N. Chu (Iowa State)
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Constrained "Modern" Floorplanning [p. 128]
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Y. Feng, D. P. Mehta (Colorado School of Mines), H. Yang (Strategic CAD Labs., Intel)
PowerPoint slides
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An Integrated Floorplanning with an Efficient Buffer Planning Algorithm [p. 136]
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Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai (Tsinghua University),
C. K. Cheng (University of California at San Diego),
J. Gu (Science & Technology, University of Hong Kong)
PowerPoint slides
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Floorplanning of Pipelined Array Modules using Sequence Pairs [p. 143]
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M. Moe, H. Schmit (Carnegie Mellon University)
PowerPoint slides
Chair: P. Groeneveld (Eindhoven)
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Efficient Steiner Tree Construction Based on Spanning Graphs [p. 152]
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H. Zhou (Northwestern University)
PowerPoint slides
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Porosity Aware Buffered Steiner Tree Construction [p. 158]
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C. J. Alpert (IBM Corporation), G. Gandham (IBM Corporation at Hopewell Junction, NY),
M. Hrkic (University of Illinois at Chicago), J. Hu (Texas A&M University),
S. T. Quay (IBM Corporation)
PowerPoint slides
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Epsilon-Optimal Minimum-Delay/Area Zero-Skew Clock
Tree Wire-Sizing in Pseudo-Polynomial Time [p. 166]
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J.-L. Tsai, T.-H. Chen (University of Wisconsin at Madison), C. C.-P. Chen (National Taiwan
University)
PowerPoint slides
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Process Variation Aware Clock Tree Routing [p. 174]
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B. Lu (Cadence Design Sys. Inc.), J. Hu (Texas A&M University),
G. Ellis (IBM Microelectronics), H. Su (IBM Austin Research Lab)
PowerPoint slides
Organizers: J. Cong (University of California at Los Angeles) and L. Pileggi (Carnegie Mellon University)
Chair: J. Cong (University of California at Los Angeles)
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An Architectural Exploration of Via Patterned Gate Arrays [p. 184]
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C. Patel, A. Cozzie, H. Schmit, L. Pileggi (Carnegie Mellon University)
PowerPoint slides
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Architecture and Synthesis for Multi-Cycle Communication [p. 190]
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J. Cong, Y. Fan, X. Yang, Z. Zhang (University of California at Los Angeles)
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Synthesis and Placement Flow for Gain-Based Programmable
Regular Fabrics [p. 197]
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B. Hu, H. Jiang, Q. Liu, M. Marek-Sadowska (University of California at Santa Barbara)
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Fishbone: A Block Level Placement and Routing Scheme [p. 204]
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F. Mo, R. K. Brayton (University of California at Berkeley)
PowerPoint slides
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