FINAL PROGRAM
The International Symposium on Physical Design
provides a high-quality forum for the exchange
of ideas and results in critical areas related
to the physical design of VLSI systems. This meeting
evolved from the ACM/SIGDA Physical Design Workshops
held during the years 1987-1996. The scope of
this symposium includes all aspects of physical
design, from interactions with behavior- and logic-level
synthesis, to back-end performance analysis and
verification.
SUNDAY, APRIL 1
5:30 - 7:00 pm Evening
Reception
MONDAY, APRIL
2
8:30 - 9:35
am Keynote: 21st Century Drivers for EDA technology
- Where We Are Headed and Why
Host: M.Wiesel
Keynote Address: Jim Hogan/Cadence
This presentation will focus on the changing face
of consumers and their effect on the designer
community, the business models, the design domains,
and subsequently, EDA technology. The main emphasis
will be on the COT market, its changing role in
the electronics industry, and its unique requirements
from the EDA solutions. The speaker will conclude
with observations on what changes are needed specifically
in the physical design area and also where the
EDA industry would like the academic community
to focus its research efforts.
9:35 - 10:00 am Break
10:00 - 11:00 am Session 1: Differences in
ASIC, COT and Processor Design
Organizer and Chair: M. Sarrafzadeh/UCLA
ASIC, Customer-Owned Tooling, and Processor Design
(invited)
Speaker: N. Nettleton/Sun
Are Classic Design Flows Suitable Below 0.18u?
(invited)
Speaker:W. Roethig/NEC
Trends in ASIC Design Flow From a Tool Vendor
Perspective (invited)
Speaker:D. Hill/Synopsys
11:00 am - 12:00 pm Session 2: Routing the
Global Interconnect Problem
Chair: H. Zhou/Synopsys
Buffered Steiner Trees for Difficult Instances
C. J. Alpert, G. Gandham, J. Hu, S. T. Quay,
A. J. Sullivan/IBM, M. Hrkic, J. Lillis/UIC, A.
B. Kahng, B. Liu/UCSD, S. S. Sapatnekar/Minnesota
An Exact Algorithm for Coupling-Free Routing
R. Kastner, E. Bozorgzadeh, M. Sarrafzadeh/UCLA
RC(L)
RC(L) Interconnect Sizing with Second Order Considerations
via Posynomial Programming
T. Lin, L. Pileggi/CMU
12:00 - 1:30 pm Lunch
1 :30 - 2:10 pm Session 3: Placement
Chair: S. Raje/Monterey
A Performance-Driven Standard-Cell Placer Based
on a Modified Force-Directed Algorithm
Y.-C. Chou, Y.-L. Lin/Tsinghua
Reporting of Standard Cell Placement Results
P. H. Madden/SUNY-Binghamton
2:10 - 3:40 pm Session 4: Manufacturing and
Design Variability, Needs and Solutions
Chair: A. B. Kahng/UCSD
PD Requirements for Alt PSM (invited)
Speaker: F.-L. Heng/IBM
Reticle Enhancement Technology Trends: Resources
and Manufacturability Implications for the Implementation
of Physical Designs (invited)
Speaker: W. Grobman/Motorola
Impact on Design of the Adoption of OPC
(invited)
Speaker: F. Schellenberg/Mentor Graphics
3:40 - 4:15 pm
Break and Meet-the-Authors for Sessions 2, 3,
and 4
4:15 - 10:45 pm
ISPD Monday Evening Event:
Napa Valley Wine Train
(and dinner)
TUESDAY, APRIL 3
9:00 - 10:10 am Session 5: Issues in the Design
of Supply Networks
Chair: D. Kirkpatrick/Intel
Power Trends and Issues in Physical Design (invited)
S. Kumar/Intel
Design of Robust Global Power and Ground Networks
S. Boyd, L Vandenberghe, A. El Gamal, S. Yun/Stanford
Decoupling Capactance Allocation for Power Supply
Noise Suppression
S. Zhao, K. Roy, C.-K. Koh/Purdue
10:10 - 10:40 am
Break and Meet-the-Authors for Session 5
10:40 - 12:10 pm Session 6: Fundamental CAD Algorithms
Chair: L. Scheffer/Cadence
Overview of Continuous Optimization Advances
and Applications to Circuit Tuning (invited)
Conn presentation, Visweswariah presentation
A. R. Conn, C. Visweswariah/IBM
Design and Analysis of Physical Design Algorithms
(invited)
M. Sarrafzadeh/UCLA
12:10 - 1:45 pm Lunch
1:45 - 2:30 pm Session 7: Multi-GHz Interconnect
Effects in Microprocessors (invited)
Chair: D.F. Wong/UT-Austin
Multi-GHz Clock Networks
P. Restle, A. E. Ruehli, S. J. Walker/IBM
2:30 pm - 3:00 pm Session 8: Poster Papers,
Brief Introductions
Chair: C.-K. Koh/Purdue
Min-Cut Partitioning with Functional Replication
for Technology Mapped Circuits using Minimum Area
Overhead
W.-K. Mak/South Florida
Maximum Current Estimation Considering Power Gating
F. Li, L. He/Wisconsin
Estimating Routing Congestion using Probabilistic
Analysis
J. Lou, S. Krishnamoorthy, H. S. Sheng/Synopsys
Dummy Feature Placement for Chemical-Mechanical
Polishing Uniformity in a Shallow Trench Isolation
Process
R. Tian/Motorola, X. Tang, D. F. Wong/UT-Austin
Slicing Floorplan Design with Boundary-Constrained
Modules
E.-C. Liu, M.-S. Lin, T.-C. Wang/Texas A&M
A Regularity-Driven Fast Gridles Detailed Router
for High Frequency Datapath Designs
S. Das/Intel, S. P. Khatri/Colorado
3:00 - 4:00 pm Poster Discussions
4:00 - 5:20 pm Session 9: Floorplanning
Chair: C. N. Chu/Iowa State
ECBL: An Extended Corner Block List with Solution
Space Including Optimum Placement
S. Zhou, S.-Q. Dong, X.-L. Hong, Y.-C. Cai/Tsinghua,
C.-K. Cheng/UCSD, J. Gu/HKUST
Revisiting Floorplan Representations
B. Yao, H. Chen, C.-K. Cheng, R. Graham/UCSD
Consistent Floorplanning with Super Hierarchical
Constraints
S. Nakatake/Kitakyushu
Rectilinear Block Packing Using O-tree Representation
Y. Pang, K. Lampert/Mindspeed, C.-K. Cheng/UCSD,
W. Xie/HP
5:20 - 5:45 pm Break and Meet-the-Authors for
Sessions 7, 8 and 9
6:00 pm - 7:00 pm Birds of a Feather Meeting:
Industry Grants and IP Rights
Chair: J. Parkhurst/Intel
My Proposal was Approved for Funding but When
am I Going to See the Money ?
Panelists: D. F. Wong/Texas, M. Burnham/Motorola,
F. Pita/SRC, A. Poskanzer/ Arizona State
7:00 pm - 10:00 pm Dinner
Dinner Speaker: S. Somekh/Applied Materials
Title: 100nm Process Technology
WEDNESDAY, APRIL 4
9:00 - 9:40 am Session 10: Predicting and Analyzing
Layout Characteristics
Chair: C. J. Alpert/IBM
Congestion Estimation During Top-down Placement
X. Yang, R. Kastner, M. Sarrafzadeh/UCLA
Interconnect Characteristics of 2.5-D System Integration
Scheme
Y. Deng, W. Maly/CMU
9:40 - 10:40 am Session 11: Design Closure
Chair: M. Pedram/USC
Hierarchical Physical Design Methodology for Multi-million
Gate Chips (invited)
W.-J. Dai/Silicon Perspective
Overcoming Wireload Model Uncertainty During Physical
Design (invited)
P. Gopalakrishnan, A. Odabasioglu, S. Raje/Monterey,
L. Pillegi/CMU
10:40 - 11:10 am Break and Meet-the-Authors
for Sessions 10 and 11
11:10 am - 12:10 pm Session 12: New Solutions
to Traditional Problems
Chair: R. Otten/Eindhoven
A Minimum Cost Path Search Algorithm Through Tile
Obstacles
Z. Xing, R. Kao/Sun
An Exact Algorithm for Solving Difficult Detailed
Routing Problems
K. Sulimma, W. Kunz/Frankfurt
Boosters for Driving Long On-chip Interconnects:
Design Issues, Interconnect Synthesis and Comparison
with Repeaters
A. Nalamalpu/Intel, W. Burleson/UMass
12:10 - 1:30 pm Lunch
1:30 - 2:35 pm Session 13: FPGA PD in DSM VLSI
Chair: D. Hill/Synopsys
Physical Design for FPGAs (invited)
Speaker: R. Jayaraman/Xilinx
A Comparative Study of Two Boolean Formulations
of FPGA Detailed Routing Constraints
G.-J. Nam, F. Aloul, K. Sakallah/Michigan,
R. Rutenbar/CMU
2:35 - 3:00 pm Break and Meet-the-Authors for
Sessions 12 and 13
3:00 - 4:05 pm Session 14: Hot Ideas in Thermal
Analysis and Optimization
Chair: P. Groeneveld/Magma
Analysis and Optimization of Thermal Effects in
VLSI (invited)
Speaker: K. Banerjee/Stanford, M. Pedram/USC
Thermal-ADI: A Linear-Time Chip-Level Dynamic
Thermal Simulation Algorithm Based on Alternating-Direction-Implicit
(ADI) Method
T.-Y. Wang, C. C.-P. Chen/Wisconsin
4:05 - 4:15 pm Closing Remarks and Door Prizes
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