List of Accepted Papers

#2 GOALPlace: Begin with the End in Mind
#4 GPU-Accelerated Inverse Lithography Towards High Quality Curvy Mask Generation
#7 Cell-Flex Metrics for Designing Optimal Standard Cell Layout With Enhanced Cell Layout Flexibility
#19 GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays
#21 Cypress: VLSI-Inspired PCB Placement with GPU Acceleration
#22 DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
#24 Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin Access
#28 Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology
#37 Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM Assistance
#38 LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes
#40 Abuttable Analog Cell Library and Automatic AMS Layout
#41 ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs
#42 HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning
#43 APR: Automated Photonic Integrated Circuit Detailed Routing with Curvy Waveguide and Adaptive Crossing Insertion
#49 LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method
#54 Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICs
#55 ML-QLS: Multilevel Quantum Layout Synthesis
#58 LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active Learning