March 12-15, 2024
National Taiwan University, Taipei, Taiwan

ISPD highlights extreme technology scaling, more-than-Moore, and physical design automation advances

The 32nd International Symposium on Physical Design (ISPD) took place March 26 to 29 online, where leading researchers and next-generation designers, from across the world, gather annually for the physical design of future chips. Advances in semiconductor fabrication process technology continue to push the limits of process lithography into the deep nanometer regime for better performance, power, and area, chasing Moore’s Law. Diverse devices have adopted heterogeneous integration to achieve better system-level power-performance cost trade-offs and higher performance.

Heterogeneous integration of multiple chips in the same package was the focus on the first day. UC Berkeley’s Professor Alberto Sangiovanni-Vincentelli’s keynote “Automated Design of Chiplets” highlighted opportunities and challenging design considerations in this promising area. “Instead of designing one monster chip, chiplets are a recent way of packaging our design, in particular coming from the need for intelligent system design,” Alberto said. Two sessions on 3D ICs, heterogeneous integration and packaging, included presentations from Technical University of Munich, Georgia Institute of Technology, National Yang Ming Chiao Tung University, Sandia National Labs, Cadence, and Synopsys, described recent advances in this area. “Everything related to 3D IC involves a big investment,” Wen-Hao Liu from Cadence Design Systems said.

Applications keep driving the requirements of extreme technology scaling. In the second keynote address, Professor Burn J. Lin, from National Tsing Hua University, explored immersion and extreme ultraviolet (EUV) lithography to show how we have now achieved single-digit nanometer dimensions for circuit elements. “Any idea is always driven by need,” Burn said when Professor Yao-Wen Chang from National Taiwan University asked about the origin of immersion lithography. “Scaling becomes very hard. We have not reached the ultimate scaling physical limit yet, but have a hard time to resolve overlay errors,” Burn said.

ISPD 2023 also foresees the need for emerging technologies in the physical design context. In the third keynote address, Professor Anima Anandkumar from Caltech and NVIDIA, detailed their research providing state-of-the-art Fourier neural operators to efficiently solve partial differential equations (PDEs) on general geometries, demonstrating benefits in computational lithography. “Compared with traditional numerical methods or optimization techniques, AI can have dramatical speedups by using GPU accelerated computing, and machine learning can potentially find faster approaches solving PDEs and other physics problems like lithography, and progressive self-training keeps improving the quality of masks,” Anima said.

In addition to machine-learning boosted physical design and design for manufacturability, hardware acceleration for electronic design automation (EDA) software, quantum computing, domain-specific computing, and hardware security are hot research topics.

The best paper this year went to Fangzhou Wang, Jinwei Liu, and Professor Evangeline F. Y. Young from the Chinese University of Hong Kong. They proposed a wiring routability pin-access solution with incremental satisfiability that was 14.7x faster than the known best solution. “Pin access is one of the most complicated sub-problems in VLSI routing. We are working on dynamic pin access analysis, capable of making adjustments after nets are routed,” Fangzhou said.

This year, ISPD honored Professor Malgorzata Marek-Sadowska, who was with the University of California, Santa Barbara. She is the first woman to receive the ISPD lifetime achievement award and an EDA pioneer involved in the development of physical design, logic synthesis, testability, modeling of electrical phenomena affected by circuit layout, power grid analysis, and timing.

Since 2005, ISPD has organized highly competitive contests to promote and advance research in placement, global routing, clock network synthesis, discrete gate sizing, detailed routing-driven placement, and hardware security. The contest this year is organized by the team led by Dr. Johann Knechtel from New York University at Abu Dhabi. It focuses on hardening physical layouts against security threats. The task is to modify hardware layouts to reduce their susceptibility to layout-level Trojan insertion. “According to the teams’ feedback, physical design in general was the more challenging part of the contest than security closure,” Johann said, revealing that trade-offs to achieve hardware security are difficult. First place went to team FDUEDA in the lab of Professor Jianli Chen at Fudan University. Second place went to team NTHU-TCLAB with Professor Ting-Chi Wang at National Tsing Hua University. Third place went to Professor Evangeline F. Y. Young's CUEDA team at the Chinese University of Hong Kong. And fourth place went to the XDSecurity-II team supervised by Professor Hailong You and Professor Cong Li at XiDian University.

3D IC Floorplanning Source: Cadence Design Systems, University of California, Berkeley, Alberto Sangiovanni-Vincentelli and Zheng Liang; Peking University, Zhe Zhou and Jiaxi Zhang.