ISPD 2024 Tentative Program

1. "MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner", Rongjian Liang, Anthony Agnesina and Haoxing Ren, (Nvidia, USA)

2. "FuILT: Full Chip ILT System With Boundary Healing", Shuo Yin, Wenqian Zhao, Li Xie, Hong Chen, Yuzhe Ma, Tsung-Yi Ho and Bei Yu (The Chinese University of Hong Kong, Hong Kong University of Science and Technology, ShenZhen Guoweixin Technology Co., Ltd, China)

3. "Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops", Yen-Yu Chen, Hao-Yu Wu, Iris Hui-Ru Jiang, Cheng-Hong Tsai and Elvis Wu (National Taiwan University)

1. "Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement", Wuxi Li, Yuji Kukimoto, Gregory Servel, Ismail Bustany and Mehrdad E. Dehkordi (AMD),

2. "Novel Airgap Insertion and Layer Reassignment for Timing Optimization Guided by Slack Dependency", Wei-Chen Tai, Min-Hsien Chung and Iris Hui-Ru Jiang (National Taiwan University),

3. "Hybrid CPU/GPU accelerating timing analysis", Tsung-Wei Huang (University of Utah),

Panelists: Andrew Kahng (UC San Diego), Bei Yu (CUHK), Eugene Liu (Siemens EDA), Keh-Jeng Chang (TSMC), I-Lun Tseng (MediaTek)

1. "Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs", Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu and Martin Wong (The Chinese University of Hong Kong, Peking University, China)

2. "3D ICs", Thunder Lay (Cadence)

3. "Chip-Package Interaction in 3D Stacks", Jun-Ho Choy (Siemens)

4. "Challenges for Automating PCB Layout", Wen-Hao Liu (NVIDIA)

1. "FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning", Hao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul and Sung Kyu Lim (National Taiwan University, Global Unichip Corp, Taiwan)

2. "Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model", Suwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyu-Myung Choi and Taewhan Kim (Seoul National University, South Korea)

3. "AI for EDA/physical design", Erick Chao (Cadence, Taiwan)

4. "AI at the Flow Level", Piyush Verma (Synopsys)

5. "Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design", Andrew Kahng (UC San Diego)

"Layout Design Automation for Heterogeneous Integration", Yao-Wen Chang (National Taiwan University)

1. "Overview on Analog Design", Jürgen Scheible(Reutlingen University)

2. "Layout Verification using Open-Source Software", Andreas Krinke (Dresden University of Technology)

3. "Overview on Analog Design", Mark Po-Hung Lin (National Yang Ming Chiao Tung University)

1. "Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint", Teng-Ping Huang and Shao-Yun Fang (National Taiwan University of Science and Technology, Taiwan)

2. "Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells", Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kaiyuan Chao, Keren Zhu, Yibo Lin and Bei Yu (The Chinese University of Hong Kong, Huawei Technologies Noah's Ark Lab, Peking University, China)

3. "IncreMacro: Incremental Macro Placement Refinement", Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin and Bei Yu (The Chinese University of Hong Kong, The Chinese University of Hong Kong, Shenzhen, China, Shanghai AI Laboratory, China, Peking University, China) (Best Paper Candidate)

4. "Timing-Driven Analytical Placement According to Expected Cell Distribution Range", Jai Ming Lin, You Yu Chang and Wei Lun Huang (National Cheng Kung University, Taiwan)

1. "Routability Booster - Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources", Bing-Xun Song, Ting Xin Lin and Yih-Lang Li (National Yang Ming Chiao Tung University, Taiwan)

2. "Novel Transformer Model Based Clustering Method for Standard Cell Design Automation", Chia-Tung Ho, Ajay Chandna, David Guan, Alvin Ho, Minsoo Kim, Yagunag Li and Haoxing Ren (Nvidia, USA) (Best Paper Candidate)

3. "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization", Chien-Pang Lu, Iris Hui-Ru Jiang, Chung-Ching Peng, Mohd Mawardi Mohd Razha and Alessandro Uber (Intel and NTU (Taiwan, Malaysia, Germany))

1. "Thermal Analysis", Alex Hung (Siemens, Taiwan)

2. "3D Heterogeneous Integration", Jim Chang (TSMC)

3. "Advanced Packaging", Hung-Ming Chen (National Yang Ming Chiao Tung University)

1. Jason Cong (University of California at Los Angeles)

2. Evangeline Young (CUHK)

3. Ting-Chi Wang (NTHU)

4. Martin D.F. Wong (Hong Kong Baptist University)

TBD, Bor-Sung Liang (MediaTek)

2. "Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems", Wei-Hsiang Tseng, Yao-Wen Chang and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)

3. "Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement", Bing-Huan Wu and Wai-Kei Mak (National Tsinghua University, Taiwan)

1. "Design Automation Challenges for Automotive", Chung-Wei Lin (National Taiwan University)

2. "Physical Design Challenges for Automotive ASICs", Goeran Jerke (Bosch)