2012 International Symposium on Physical Design

With a Tribute to Professor C.-L. Liu

Napa Valley, California, March 25-28, 2012



Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS

Additional support from ATopTech, Cadence, IBM Research,

Institute of Information and Computing Machinery, Industrial Technology Research Institute,

Intel Corporation, Mentor Graphics, National Taiwan University,

Oracle, SpringSoft, Synopsys, and TSMC


The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI and biological systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing.


Regular presentations are 30 minutes. Short presentations (S) are 15 minutes.


SUNDAY, March 25


5:30 - 7:00 pm: Evening Reception     


MONDAY, March 26


8:30 - 9:45 am: Welcome and Keynote Address

Host: Jiang Hu (Texas A&M University)


Keynote Talk: Lithography Till the End of Moore's Law

Burn Lin (TSMC) [slides]


9:45 - 10:15 am: Morning Break


10:15 am - 12:15 pm Session 1: Advanced Processes

Chair: Markus Olbrich (University of Hannover)

(Invited talk) Design-Aware Lithography
Shayak Banerjee, Kanak Agrawal, Sani Nassif
(IBM Research)

Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication (Best Paper Nominee)
Shao-Yun Fang, Wei-Yu Chen and Yao-Wen Chang

A Polynomial Time Exact Algorithm for Self-Aligned Double Patterning Layout Decomposition
Zigang Xiao, Yuelin Du, Hongbo Zhang and Martin D. F. Wong [slides]

Flexible Self-aligned Double Patterning Aware Detailed Routing with Prescribed Layout Planning
Jhih-Rong Gao and David Z. Pan

12:15 - 1:45 pm: Lunch


1:45 - 3:15 pm Session 2: Emerging Challenges and Technologies

Chair: David Pan (UT-Austin)

(Invited talk) Integration, Architecture, and Applications of 3D CMOS-Memristor Circuits
Tim Cheng
(UCSB) [slides]

A Fast Estimation of SRAM Failure Rate Using Probability Collectives

Fang Gong, Sina Basir-Kazeruni, Lara Dolecek and Lei He [slides]

Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips
Tsung-Wei Huang, Jia-Wen Chang and Tsung-Yi Ho

3:15 - 3:45 pm: Afternoon Break

3:45 - 5:45 pm Session 3: Commemoration for Professor C.-L. Liu
Chair: Yao-Wen Chang (National Taiwan University)

(Invited talk) Transformation from Ad Hoc EDA to Algorithmic EDA
Jason Cong

(Invited talk) On Simulated Annealing in EDA
Martin Wong

(Invited talk) On Pioneering Nanometer-Era Routing Problems
Tong Gao
and Prashant Saxena (Synopsys)

(Invited talk) I attended the Nineteenth Design Automation Conference
C.-L. Liu
(National Tsing Hua University)

5:45 - 6:15 pm: Reception


6:15 - 8:45 pm: Dinner Banquet
Honoring Prof. C.-L. Liu: Everybody Loves Dave



TUESDAY, March 27


8:30 - 10:00 am Session 4: Analog, Datapath, and Detailed Placement
Chair:  Ismail Bustany (Mentor Graphics)

Routability-driven Placement Algorithm for Analog Integrated Circuits
Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin and Soon-Jyh Chang [slides]

Keep it Straight: Teaching Placement how to Better Handle Designs with Datapaths (Best Paper Nominee)
Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles Alpert, Earl Swartzlander and David Z. Pan

Mixed Integer Programming Models for Detailed Placement
(Best Paper Nominee)
Shuai Li and Cheng-Kok Koh

10:00 - 10:30 am: Morning Break


10:30 am - 12:15 pm Session 5: Power and Thermal Modeling and Optimization
Chair: Charles Liu (TSMC)

(Invited talk) Power-Grid (PG) Analysis Challenges for Large Microprocessor Designs (Our Experience with Oracle Sparc Processor Designs)
Alexander Korobkov

Efficient On-line Module-Level Wake-Up Scheduling for High Performance Multi-Module Designs
Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu and Shih-Chieh Chang [slides]

Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph

Chung-Kuan Cheng, Peng Du, Andrew Kahng and Shih-Hung Weng [slides]


(S) TSV-Constrained Micro-Channel Infrastructure Design for Cooling Stacked 3D-ICs
Bing Shi and Ankur Srivastava [slides]


12:15 - 1:45 pm: Lunch Break

1:45 - 3:45 pm Session 6: Clocking and Routing

Chair: Yiyu Shi (Missouri University of Science and Technology)


(Invited talk) Construction of Minimal Functional Skew Clock-trees
Venky Ramachandran
Mentor Graphics) [slides]

Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral Clustering
Chih-Long Chang, Iris Hui-Ru Jiang, Yu-Ming Yang, Yu-Wen Tsai and Sheng-Hua Chen

On Constructing Low Power and Robust Clock Tree via Slew Budgeting
Yeh-Chi Chang, Chun-Kai Wang and Hung-Ming Chen

Optimizing Antenna Area and Separators in Layer Assignment of Multi-Layer Global Routing

Wen-Hao Liu and Yih-Lang Li

3:45 - 4:15 pm: Afternoon Break

4:15 - 5:45 pm Session 7: Gate Sizing
Chair: Ozdal Mustafa (Intel)

Simultaneous Clock and Data Gate Sizing Algorithm with Common Global Objective
Gregory Shklover and Ben Emanuel [slides]

Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions
Andrew B. Kahng and Seokhyeong Kang

(Invited talk) The ISPD-2012 Discrete Cell Sizing Contest and Benchmark Suite
Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven Burns, Gustavo Wilke and Cheng Zhuo
(Intel) [slides]

6:15 - 8:45 pm: Dinner Banquet



8:30 - 10:00 am Session 8: Congestion-Driven Logic and Physical Synthesis
Zhuo Li (IBM)

(Invited talk) Towards Layout-Friendly High-Level Synthesis
Jason Cong
(UCLA) [slides]

(Invited talk) Synthesis for Advanced Nodes: An Industry Perspective
Abhijeet Chakraborty and Janet Olson
(Synopsys) [slides]

(Invited talk) Reality-Driven Physical Synthesis
Patrick Groeneveld
(Magma Design Automation) [slides]

10:00 - 10:30 am: Morning Break

10:30 am - 12:00 pm Session 9: Floorplanning and Mixed-Size Placement

Chair: Ting-Chi Wang (National Tsing Hua University)

Optimal Slack-Driven Block Shaping Algorithm in Fixed-Outline Floorplanning (Best Paper Nominee)
Jackey Yan and Chris Chu

(S) Scalable Hierarchical Floorplanning for Fast Physical Prototyping of Systems-on-Chip
Renshen Wang and Nimish Shah

MAPLE: Multilevel Adaptive PLacEment for Mixed-Size Designs (Best Paper Nominee)
Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov and Shyam Ramji

A Size Scaling Approach for Mixed-size Placement
Kalliopi Tsota, Cheng-Kok Koh and Venkataramanan Balakrishnan

12:00 - 12:10 pm: Closing Remarks


12:10 - 1:30 pm: Lunch

2:00 - 3:30 pm: Winery Tour and Wine Tasting