2010 International Symposium on Physical Design
Marriott Fisherman's Wharf, San Francisco, California, USA
March 14 - 17, 2010

Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS
Additional support from Cadence, IBM Research, Intel Corporation, Mentor Graphics, SpringSoft, Sun, and Synopsys

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance analysis and verification.

Each regular paper presentation runs 25 minutes. Each invited talk is 30 minutes. The ISPD'10 Best Paper Award nominees are marked with an asterisk (*).

SUNDAY, March 14

5:30 - 7:00 pm Evening Reception

MONDAY, March 15

8:30 - 9:40 am Welcome and Keynote Address
Host: Prashant Saxena / Synopsys
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(Keynote Talk) Physical Design of Biological Systems
Louis K. Scheffer from Howard Hughes Medical Institute
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9:40 - 10:10 am Morning Break

10:10 am - 12:10 pm Session 1: Modern Physical Design Challenges
Chair: Lars Hagen / Cadence

(Invited Talk) Going with the Flow: Bridging the Gap between Theory and Practice in Physical Design
Patrick Groeneveld from Magma
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(Invited talk) Design Planning Trends and Challenges
Neeraj Kaul from Synopsys
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(Invited talk) Physical Design Challenges beyond the 22nm Node
Sani Nassif and Kevin Nowka from IBM
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(Invited talk) Challenges and Opportunities in Optimization of Automotive Electronics
Serge Leef from Mentor Graphics
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12:10 - 2:00 pm Lunch

2:00 - 4:15 pm Session 2: Advances in Routing
Chair: Mustafa Ozdal / Intel

(Invited talk) What Makes a Design Difficult to Route
Charles Alpert, Zhuo Li, Michael Moffitt, Gi-Joon Nam, Jarrod Roy, and Gustavo Tellez from IBM
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* FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
Gaurav Ajwani, Chris Chu and Wai-Kei Mak
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Completing High-Quality Global Routes
Jin Hu, Jarrod Roy and Igor Markov
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(Invited talk) Thinking Outside of the Chip
John Park from Mentor Graphics
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* B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing
Lijuan Luo, Tan Yan, Qiang Ma, Martin Wong and Toshiyuki Shibuya
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4:15 - 4:45 pm Afternoon Break

4:45 - 6:10 pm Session 3: Analog Design Automation
Chair: Lei He / UCLA

(Invited talk) Analog Layout Synthesis: What's Missing?
Rob Rutenbar from University of Illinois
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(Invited talk) Design Platform for Electrical and Physical Co-Design of Analog Circuits
Mar Hershenson from Magma

Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits
Michael Eick, Martin Strasser, Helmut Graeb and Ulf Schlichtmann
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6:10 - 9:00 pm: Dinner Banquet

TUESDAY, March 16

8:30 - 10:25 am Session 4: Physical Design for 3D ICs
Chair: Sung Kyu Lim / Georgia Institute of Technology

(Invited talk) Adding a New Dimension to Physical Design
Sachin Sapatnekar from University of Minnesota
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(Invited talk) Physical Design Implementation for 3D IC: Methodology and Tools
Dave Noice and Vassilios Gerousis from Cadence
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(Invited talk) Efficient Design Practices for Thermal Management of a TSV Based 3D IC System
Zongwu Tang from Synopsys
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An Analytical Placer for Mixed-Size 3D Placement
Jason Cong and Guojie Luo
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10:25 - 10:55 am Morning Break

10:55 am - 12:35 pm: Session 5: Physical Synthesis
Chair: Igor Markov / University of Michigan

Logical and Physical Restructuring of Fan-In Trees
Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi Reddy, Ruchir Puri and Minsik Cho
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Ultra-Fast Interconnect Driven Cell Cloning for Minimizing Critical Path Delay
Zhuo Li, David Papa, Charles Alpert, Shiyan Hu, Weiping Shi, Cliff Sze and Ying Zhou
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ITOP: Integrating Timing Optimization within Placement
Natarajan Viswanathan, Gi-Joon Nam, Jarrod Roy, Zhuo Li, Charles Alpert, Shyam Ramji and Chris Chu
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Physical Synthesis of Bus Matrix for High Bandwidth Low Power On-Chip Communications
Renshen Wang, Evangeline Young, Ronald Graham and Chung-Kuan Cheng
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12:35 - 2:00 pm Lunch

2:00 - 3:40 pm Session 6: Design for Manufacturing
Chair: Ting-Chi Wang / National Tsing-Hua University

Dummy Fill Optimization for Enhanced Manufacturability
Yaoguang Wei and Sachin Sapatnekar
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Density Gradient Minimization with Coupling-Constrained Dummy Fill for CMP Control
Huang-Yu Chen, Szu-Jui Chou and Yao-Wen Chang
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Total Sensitivity Based DFM Optimization of Standard Library Cells
Yongchan Ban, Savithri Sundareswaran and David Z. Pan
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A Matching Based Decomposer for Double Patterning Lithography
Yue Xu and Chris Chu
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3:40 - 4:10 pm Afternoon Break

4:10 - 5:40 pm Session 7: Advances in Clock Tree Designs and ISPD'10 Clock Tree Synthesis Contest
Chair: Cliff Sze / IBM Research

* Skew Management of NBTI Impacted Gated Clock Trees
Ashutosh Chakraborty and David Z. Pan
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Accurate Clock Mesh Sizing via Sequential Quadratic Programming
Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu and Peng Li
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(Invited talk) ISPD 2010 High Performance Clock Network Synthesis Contest: Benchmark Suite and Results
Cliff Sze from IBM
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6:00 - 9:00 pm: Dinner Banquet


8:30 - 10:40 am Session 8: Performance and Reliability Optimization
Chair: Linda Huaizhi Wu / Synopsys

(Invited talk) Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor
Rupesh Shelar and Marek Patyra from Intel
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Interconnect Power and Delay Optimization by Dynamic Programming in Gridded Design Rules
Konstantin Moiseev, Avinoam Kolodny and Shmuel Wimer
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Performance Study of VeSFET-Based, High-Density Regular Circuits
Yi-Wei Lin, Malgorzata Marek-Sadowska and Wojciech Maly
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A Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nano-Scale Systems
Yufu Zhang, Bing Shi and Ankur Srivastava
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Optimal Wiring Topology for Electromigration Avoidance Considering Multiple Layers and Obstacles
Iris Hui-Ru Jiang, Hua-Yu Chang and Chih-Long Chang
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10:40 - 11:10 am Morning Break

11:10 am - 12:25 pm Session 9: Clustering and Biochip Placement & Routing
Chair: Jens Lienig / Dresden University of Technology

* SafeChoice: A Novel Clustering Algorithm for Wirelength-Driven Placement
Jackey Z. Yan, Chris Chu and Wai-Kei Mak
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Droplet-Routing-Aware Module Placement for Cross-Referencing Biochips
Zigang Xiao and Evangeline F. Y. Young
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A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips
Tsung-Wei Huang and Tsung-Yi Ho
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12:25 - 12:40 pm Closing Remarks

12:40 - 2:00 pm Lunch