2009 International Symposium on Physical Design
Marriott Mission Valley, San Diego, California, USA
March 29 - April 1, 2009

Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE/CAS and IEEE/CEDA
Additional support from Cadence, IBM Research, Sun Microsystems, SpringSoft, Synopsys, and Tela Innovations

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance analysis and verification.

Regular paper presentations run 25 minutes. Invited talks are 30 minutes. The ISPD'09 Best Paper Award nominees are marked with an asterisk (*).


5:30 - 7:00 pm Evening Reception


8:30 - 9:30 am Welcome and Keynote Address
Host: Gi-Joon Nam (IBM Research)
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(Keynote Talk) One Look into the Future of CMOS Chip Design
Carl J. Anderson (IBM)

9:30 - 10:00 am Morning Break

10:00 - 11:45 am Session 1: Global Layout Planning
Chair: Cheng-Kok Koh (Purdue University)

(Invited Talk) Early Stage Analysis for Power Distribution
Kai Wang, Aveek Sarkar, Norman Chang and Shen Lin
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Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs
Wan-Ping Lee, Diana Marculescu and Yao-Wen Chang
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Multi-voltage Floorplan Design with Optimal Voltage Assignment
Zaichen Qian and Evangeline Young
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Robust Interconnect Communication Capacity Algorithm by Geometric Programming
Jifeng Chen, Jin Sun and Janet Wang
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11:45 am - 1:30 pm Lunch

1:30 - 3:10 pm Session 2: Physical Synthesis and Circuit Optimization
Chair: Lars Hagen (Cadence)

* A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
Yifang Liu and Jiang Hu
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On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion
Ashutosh Chakraborty and David Z. Pan
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Fast Buffering for Optimizing Worst Slack and Resource Consumption in Repeater Trees
Christoph Bartoschek, Stephan Held, Dieter Rautenbach and Jens Vygen
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On Improving Optimization Effectiveness in Interconnect-Driven Physical Synthesis
Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin and Mahesh Iyer
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3:10 - 3:40 pm Afternoon Break

3:40 - 5:40 pm Session 3: Nanotechnology: CMOS and Beyond
Chair: Lei He (UCLA)

(Invited Talk) Will 22nm Be Our Catch-22? Design and CAD Challenges
Ruchir Puri (IBM)

(Invited Talk) New Strategies for Gridded Physical Design in 32nm Technologies and Beyond
Stephen P. Kornachuk and Michael C. Smayling (Tela Innovations)
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(Invited Talk) Vertical Slit Transistor-based Integrated Circuits (VeSTICs) Paradigm
Wojciech Maly (Carnegie Mellon University)

(Invited Talk) Graphene Based Transistors: Physics, Status and Future Perspectives
Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar and S. Hadi Rasouli (UC Santa Barbara)


8:30 - 10:10 am Session 4: Analog Design: Tools and Methodologies
Chair: Dave Noice (Cadence)

(Invited Talk) Accelerated Design of Analog, Mixed-Signal Circuits with Titan
Anirudh Devgan (Magma)

(Invited Talk) Physical Design Methodology for Analog Circuits in a System-on-a-Chip Environment
Eric Soenen (TSMC)

(Invited Talk) Constraint-driven Design - The Next Step Towards Analog Design Automation
Goeran Jerke (Robert Bosch GmbH) and Jens Lienig (Dresden University of Technology)
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10:10 - 10:40 am Morning Break

10:40 - 12:00 pm: Session 5: Layout Optimization for FPGAs and Regular Fabrics
Chair: Bill Halpin (Synopsys)

* Transistor-Level Layout of High-Density Regular Circuits
Yi-Wei Lin, Malgorzata Marek-Sadowska and Wojciech Maly
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Physical Optimization for FPGAs Using Post-Placement Topology Rewriting
Val Pevzner, Andrew Kennings and Andy Fox
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A Routing Approach to Reduce Glitches in Low Power FPGAs
Quang Dinh, Deming Chen and Martin D. F. Wong
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12:00 - 1:30 pm Lunch

1:30 - 3:10 pm Session 6: Manufacturability and Yield Enhancement
Chair: Jiang Hu (Texas A&M University)

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization
Kun Yuan, Jae-Seok Yang and David Z. Pan
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An Automatic Optical-Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization
Yang-Shan Tong, Chia-Wei Lin and Sao-Jie Chen
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Redundant Via Insertion with Wire Bending
Kuang-Yao Lee, Shing-Tung Lin and Ting-Chi Wang
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Wire Shaping Is Practical
Hongbo Zhang, Liang Deng, Kai-Yuan (Kevin) Chao and Martin D. F. Wong
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3:10-3:40 pm Afternoon Break

3:40-5:05 pm Session 7: Clocking and the ISPD'09 Clock Network Synthesis Contest
Chair: Cliff Sze (IBM)

(Invited Talk) Industrial Clock Synthesis
Pei-Hsin Ho (Synopsys)
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An Algorithm for Routing with Capacitance/Distance Constraints for Clock Distribution in Microprocessors
Rupesh Shelar
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(Invited Talk) ISPD'09 Clock Network Synthesis Contest Results
Cliff Sze (IBM)
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8:30 - 10:10 am Session 8: Advances in Routing
Chair: Tong Gao (Synopsys)

Critical-Trunk-based Obstacle-Avoiding Rectilinear Steiner Tree Routing for Delay and Slack Optimization
Yen-Hung Lin, Shu-Hsin Chang and Yih-Lang Li
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Layer Assignment for Via Optimization in Multi-layer Global Routing
Tsung-Hsien Lee and Ting-Chi Wang
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A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment
Shiyan Hu, Zhuo Li and Charles J. Alpert
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Diffusion-Driven Congestion Reduction for Substrate Topological Routing
Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta and Xian-Long Hong
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10:10am - 10:40am Morning Break

10:40 - 12:00 pm Session 9: Post-Si Prediction and Debug
Chair: Li-C. Wang (UC Santa Barbara)

(Invited Talk) The Challenges of Correlating Silicon and Models in High Variability CMOS Process
Robert C. Aitken (ARM)
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* Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction
Qunzeng Liu and Sachin S. Sapatnekar
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A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations
Chien-Pang Lu, Mango C.-T. Chao, Chen-Hsing Lo and Chih-Wei Chang
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12:00 - 12:15 pm Closing Remarks