2008 International Symposium on Physical Design
Embassy Suite Portland Downtown, Portland, Oregon
April 13-16, 2008

Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS
Additional support from IEEE/CEDA, Cadence, eASIC, IBM, Magma, Mentor, Pyxis, SRC, Sun and Synopsys

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance analysis and verification.

Regular paper presentations run 25 minutes. Invited talks are 30 minutes.


5:30 - 7:00 pm Evening Reception


8:30 - 9:30 am Welcome and Keynote Address
Host: David Pan/University of Texas at Austin
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(Keynote Talk) Design or Manufacturing: Which will be the best driver for the future of the semiconductor roadmap?
Antun Domic from Synopsys
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9:30 - 10:00 am Morning break

10:00 - 11:40 am Session 1: Physical Optimization Techniques with Buffering and Gate Sizing
Chair: Phiroze Parakh (Mentor Graphics)

RUMBLE: An Incremental Timing-driven Physical Synthesis Optimization Algorithm
David A. Papa, Tao Luo, Michael D. Moffitt, C. N. Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert and Igor L. Markov
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Robust Gate Sizing via Mean-Excess Delay minimization
Jason Cong, John Lee and Lieven Vandenberghe
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Multi-Scenario Buffer Insertion in Multi-core Processor Designs
Yifang Liu, Jiang Hu and Weiping Shi
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Blockage and Voltage Island-Aware Dual-Vdd Buffered Tree Construction
Bruce Tseng and Hung-Ming Chen
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12:00 - 1:30 pm Lunch

1:30 - 3:10 pm Session 2: Advances in Placement
Chair: Bill Halpin (Synplicity)

Metal-Density Driven Placement for CMP Variation and Routability
Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang
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Highly Efficient Gradient Computation for Density Constrained Analytical Placement Problems
Jason Cong and Guojie Luo
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Abacus: Fast Legalization of Standard Cell Circuits with Minimal Movement
Peter Spindler, Ulf Schlichtmann and Frank M. Johannes
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3-D Floorplanning Using Labeled Tree and Dual Sequences
Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald Graham and Chung-Kuan Cheng
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3:10 - 3:40 pm Afternoon break

3:40 - 5:20 am Session 3: Statistical and Physical Design for Manufacturability - Act II
Chair: Hidetoshi Onodera (Kyoto University)

(Invited talk) Variations, Margins, and Statistics
Patrick McGuinness
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(Invited talk) Implications of Device Timing Variability on Full Chip Timing
Ed Grochowski, Murali Annavaram and Paul Reed

(Invited talks) How To Get Real MAD
Andrew B. Kahng

(Invited talks) A Robust Approach to Lithography Friendly Design Implementation
Phiroze N. Parakh and Shankar Krishnamoorthy
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6:30 - 9:30 pm: Dinner Banquet


8:30 - 10:10 am Session 4: Interconnect Synthesis and Structured ASIC
Chair: Igor Markov (University of Michigan)

(Invited talk) Fast Interconnect Synthesis with Layer Assignment
Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay and Paul G. Villarrubia
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(Invited talk) RF Interconnects for Communications On-Chip
M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong and Glenn Reinman
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(Invited Talk) Placement Challenges for Structured ASICs
Herman Schmit, Amit Gupta and Radu Ciobanu
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10:10 - 10:40 pm Morning break

10:40 - 12:00 pm: Session 5: Logic Optimizations for Physical Synthesis
Chair: Andrew Kennings (U of Waterloo)

A Framework for Layout-level Logic Restructuring
Hosung (Leo) Kim and John Lillis
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Optimizing Non-Monotonic Interconnect Using Functional Simulation and Logic Restructuring
Stephen M. Plaza, Igor L. Markov and Valeria Bertacco
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Reap What You Sow: Spare Cells for Post-Silicon Metal Fix
Kai-hui Chang, Igor L. Markov and Valeria Bertacco
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12:00 - 1:30 pm Lunch

1:30 - 3:10 pm Session 6: Advances in Routing
Chair: Yao-Wen Chang (National Taiwan U)

Optimal Post-Routing Redundant Via Insertion
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang and Kai-Yuan Chao
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Efficient Multilayer Routing Based on Obstacle-Avoiding Preferred Direction Steiner Tree
Chih-Hung Liu, Yao-Hsin Chou, Shih-Yi Yuan and Sy-Yen Kuo
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An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction
Jieyi Long, Hai Zhou and Seda Ogrenci Memik
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Non-Slicing Floorplanning-Based Crosstalk Reduction on Gridless Track Assignment for a Gridless Routing System with Fast Pseudo-Tile Extraction
Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin and Wen-Nai Cheng
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3:10-3:40 pm Afternoon break

3:40-5:10 pm Session 7: Modern Global Routing Issues and ISPD'08 Global Routing Contest
Chair: Gi-Joon Nam (IBM)

(Invited Talk) Issues in Global Routing
William Swartz
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The Coming of Age of (Academic) Global Routing
Michael D. Moffitt, Jarrod A. Roy and Igor L. Markov
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ISPD'08 Global Routing Contest Results
Gi-Joon Nam, Cliff Sze and Mehmet Yildiz
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6:30 - 9:30 pm: Dinner Banquet


8:30 - 10:10 am Session 8: Electrical Issues and Clock Network Design in Physical Synthesis
Chair: Kai-Yuan (Kevin) Chao (Intel)

Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
Takashi Enami, Shinyu Ninomiya and Masanori Hashimoto
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Stress Aware Layout Optimization
Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw and Kanak Agarwal
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Discrete Buffer and Wire Sizing for Linked-based Non-tree Clock Networks
Rupak Samanta, Jiang Hu and Peng Li
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Activity and Register Placement Aware Gated Clock Network Design
Weixiang Shen, Yici Cai, Xianlong Hong and Jiang Hu
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10:10am - 10:40am Morning Break

10:40 - 12:00 pm Session 9: Physical Design for Bio-Microfluidics
Chair: Prashant Saxena (Synopsys)

(Invited Talk) Automated Design of Digital Microfluidic Lab-on-Chip under Pin-Count Constraints
Tao Xu and Krishnendu Chakrabarty
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(Invited Talk) Physical Design Issues in Biofluidic Microchips
Tamal Mukherjee, Anton Pfeiffer and Steinar Hauan

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A High-Performance Droplet Router for Digital Microfluidic Biochips
Minsik Cho and David Z. Pan
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12:00 - 1:00 pm Closing Remarks & Lunch


Please register on-line at http://www.ispd.cc by March 12th, 2008 for the early registration discount rates.

Registration Rates













ISPD will be held at the Embassy Suites Portland Downtown Hotel, in Portland, Oregon. The hotel is located in the downtown area near the Oregon Convention Center.

Embassy Suites Portland Downtown
Room Rate: $159/single, $169/double
Reserve By: March 12, 2008
Registration code: ACN (either on the web or calling)
Reservations may be made via calling 1-800-EMBASSY or online via www.embassysuites.com. Be sure to mention the group code when calling. If you make reservations online, please enter ACN in the Group/Convention Code section.
Airport Shuttle: contact the hotel for a reservation.
Reserve early to give yourself the best chance of getting a room.