March 26-29, 2023
Online with virtual participation

ISPD 2023 Program

All times in Pacific Daylight Time (PDT = GMT-7). Central Europe (CEST) = PDT + 9. Taiwan/China = PDT + 15.

Across the three days for ISPD 2023, we have 3 keynotes, 13 accepted papers, 22 invited talks, one panel on Wednesday with 5 panelists, 3 speakers with longer talks for Professor Marek-Sadowska's commemorative session, and finally the ISPD 2023 contest results.

Sunday, March 26, 2023

6:00 - 8:00 pm PDT. Sunday Social Chit-Chat and Welcome

Meet and greet cocktail hours on Gather.Town with the general chair of the organizing committee, David Chinnery (Siemens EDA).

Day 1 Monday, March 27, 2023

7:00 - 8:00 am PDT. Opening Session and First Keynote

Chair: David Chinnery (Siemens EDA)

"Automated Design of Chiplets", Alberto Sangiovanni-Vincentelli (University of California at Berkeley)

8:00 - 8:15 am PDT. Break

8:15 - 9:30 am PDT. Session on Routing

1. "FastPass: Fast Pin Access Analysis with Incremental SAT Solving", Fangzhou Wang, Jinwei Liu, Evangeline F. Y. Young (The Chinese University of Hong Kong), best paper candidate

2. "Pin Access-Oriented Concurrent Detailed Routing", Yun-Jhe Jiang, Shao-Yun Fang (National Taiwan University of Science and Technology)

3. "Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits", Hao Chen, Kai-Chieh Hsu, Walker Turner, Po-Hsuan Wei, Keren Zhu, David Pan, Haoxing Ren (University of Texas at Austin, Princeton University, NVIDIA)

4. "Voltage-Drop Optimization Through Insertion of Extra Stripes To A Power Delivery Network", Jai Ming Lin, Yu Tien Chen, Yang Tai Kung, Hao Jia Lin (National Cheng Kung University)

5. "NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model", Mark Ho (NVIDIA)

9:30 - 9:45 am PDT. Break

9:45 - 10:30 am PDT. Session 1 on 3D ICs, heterogeneous integration, and packaging

1. "FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines", Meng Lian, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann (Technical University of Munich)

2. "On Legalization of Die Bonding Bumps and Pads for 3D ICs", Sung-Kyu Lim (Georgia Institute of Technology)

3. "Reshaping System Design in 3D Integration: Perspectives and Challenges", Hung-Ming Chen (National Yang Ming Chiao Tung University)

10:30 - 10:45 am PDT. Break

10:45 - 11:30 am PDT. Session 2 on 3D ICs, heterogeneous integration, and packaging

1. "Co-design for Heterogeneous Integration: A Failure Analysis Perspective", Erica Douglas (Sandia National Labs)

2. "Goal Driven PCB Synthesis Using Machine Learning and Cloud Scale Compute", Taylor Hogan (Cadence Design Systems)

3. "Gate-All-Around Technology is Coming. What’s Next After GAA?", Victor Moroz (Synopsys)

11:30 - 11:45 am PDT. Break

11:45 - 1:00 pm PDT. Session on Analog Design

1. "VLSIR & Friends - Programming Analog Circuits & Layouts, for the People Who Know How to Design Them", Dan Fritchman (UC Berkeley)

2. "Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities", David Pan (UT Austin)

3. "Learning from the Implicit Functional Hierarchy in an Analog Netlist", Helmut Graeb (Technical University of Munich)

4. "The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues", Sachin Sapatnekar (University of Minnesota)

5. "Analog Layout Automation On Advanced Process Technologies", Soner Yaldiz (Intel Corporation)

1:00 - 1:30 pm PDT. Chit-Chat on Gather.Town

Day 2 Tuesday, March 28, 2023

7:00 - 7:50 am PDT. Second Keynote

"Immersion and EUV Lithography: Two Pillars to Sustain Single-Digit Nanometer Nodes", Burn J. Lin (National Tsing Hua University)

8:00 - 9:15 am PDT. Session on DFM, Reliability, and Electromigration

1. "Advanced Design Methodologies for Directed Self-Assembly", Shao-Yun Fang (National Taiwan University of Science and Technology)

2. "Challenges for Interconnect Reliability: from Element to System Level", Olalla Varela Pedreira (IMEC)

3. "Combined Modeling of Electromigration, Thermal and Stress Migration in AC Interconnect Lines", Susann Rothe, Jens Lienig (Dresden University of Technology)

4. "Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects", Nestor Evmorfopoulos (University of Thessaly)

5. "A Novel Methodology for Electromigration Assessment in On-chip Power Grids with Non-uniform Temperature Distribution: Simulations vs. Measurements", Armen Kteyan (Siemens EDA)

9:15 - 9:30 am PDT. Break

9:30 - 10:30 am PDT. Session on Placement

1. "Placement Initialization via Sequential Subspace Optimization with Sphere Constraints", Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang (National Chung Hsing University, University of California San Diego), best paper candidate

2. "DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality Using Generative Adversarial Learning", Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, Sung Kyu Lim (Georgia Institute of Technology, NVIDIA)

3. "AutoDMP: Automated DREAMPlace-based Macro Placement", Anthony Agnesina (NVIDIA)

4. "Assessment of Reinforcement Learning for Macro Placement", Andrew B. Kahng (University of California at San Diego)

10:30 - 10:45 am PDT. Break

10:45 - 11:30 am PDT. Session on New Computing Techniques and Accelerators

1. "GPU Acceleration in Physical Synthesis", Evangeline Young (Chinese University of Hong Kong)

2. "Efficient Runtime Power Modeling with On-Chip Power Meters", Zhiyao Xie (Hong Kong University of Science and Technology)

3. "Pseudonym: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs", Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan (University of Texas at Austin, Intel Corporation)

11:30 - 11:45 am PDT. Break

11:45 - 1:00 pm PDT. Lifetime Achievement Commemoration for Professor Malgorzata Marek-Sadowska [Biography]

1. "Building Oscillatory Neural Networks: AI Applications and Physical Design Challenges", Aida Todri-Sanial (Eindhoven University of Technology)

2. "Optimization of an AI SoC with a Compiler-Assisted Virtual Design Platform", Shih-Chieh Chang (National Tsing Hua University)

3. "Challenges and Opportunities for Computing-in-Memory Chips", Xiang Qiu (East China Normal University)

1:00 - 1:45 pm PDT. Chit-Chat on Gather.Town with Professor Malgorzata Marek-Sadowska

Day 3 Wednesday, March 29, 2023

7:00 - 7:50 am PDT. Third Keynote

"Neural Operators for Solving PDEs and Inverse Design", Anima Anandkumar (NVIDIA / Caltech)

7:50 - 8:00 am PDT. Break

8:00 - 8:45 am PDT. Session on Quantum Computing

1. "Quantum Challenges for EDA", Leon Stok (IBM Corporation)

2. "Developing Quantum Workloads for Workload-Driven Co-Design", Anne Matsuura (Intel Corporation)

3. "MQT QMAP: Efficient Quantum Circuit Mapping", Robert Wille (Technical University of Munich)

8:45 - 9:00 am PDT. Break

9:00 - 10:15 am PDT. Panel on EDA for domain specific computing

1. "Software-Driven Design for Domain-Specific Compute", Desmond Kirkpatrick (Intel Corporation)

2. "Google Investment in Open Source Custom Hardware Development Including No-Cost Shuttle Program", Tim Ansell (Google)

3. "A Case for Open-Source EDA Verticals", Zhiru Zhang (Cornell University)

4. "Addressing the EDA Roadblocks for Domain-Specific Compilers: an Industry Perspective", Alireza Kaviani (AMD)

5. "High-level Synthesis for Domain Specific Computing", Deming Chen (University of Illinois Urbana-Champaign)

10:15 - 10:30 am PDT. Break

10:30 - 11:30 am PDT. Session on hardware security and bug fixing

1. "Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks", Jhih-Wei Hsu, Kuan-Cheng Chen, Yan-Syuan Chen, Yu-Hsiang Lo, Yao-Wen Chang (National Taiwan University)

2. "Security Closure of IC Layouts Against Hardware Trojans", Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young, (The Chinese University of Hong Kong, New York University Abu Dhabi)

3. "X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks", Saideep Sreekumar, Mohammed Ashraf, Mohammed Nabeel, Ozgur Sinanoglu, Johann Knechtel (New York University Abu Dhabi)

4. "Validating the Redundancy Assumption for HDL from Code Clone’s Perspective", Jianjun Xu, Jiayu He, Jingyan Zhang, Deheng Yang, Jiang Wu, Xiaoguang Mao (National University of Defense Technology)

11:30 - 11:45 am PDT. Break

11:45 - 12:45 pm PDT. ISPD 2023 Contest

Chair: Iris Hui-Ru Jiang (National Taiwan University)

"Benchmarking Security Closure of Physical Layouts: ISPD 2023 Contest", Johann Knechtel (New York University)

"Closing Remarks and Outlook to ISPD 2024", Iris Hui-Ru Jiang (ISPD 2024 General Chair)

12:45 - 1:30 pm PDT. Farewell Chit-Chat on Gather.Town