March 26-29, 2023
Online with virtual participation

ISPD Lifetime Achievement Award

This award is given to individuals who have made outstanding contributions to the field of physical design automation over multiple decades. The purpose is to recognize their lifetime of achievements and contributions in terms of research work, education, and professional service.

The 2023 International Symposium on Physical Design pays tribute to Prof. Malgorzata Marek-Sadowska for her contributions to the physical design community.

Malgorzata Marek-Sadowska received an MS degree in Applied Mathematics (1971) and a PhD degree in Electrical Engineering (1976) from Politechnika Warszawska (Technical University of Warsaw), Poland.

From 1976 to 1982 she was an assistant professor at the Institute of Electron Technology at the Technical University of Warsaw. She was a research engineer at the Electronics Research Laboratory, University of California, Berkeley, from 1982 until 1990, when she joined the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, as a professor.

Professor Marek-Sadowska was a member of numerous technical committees, including the Technical Committee of the International Conference on Computer Aided Design, the Technical Committee of the Design Automation Conference, and the Technical Committee of the International Symposium on Physical Design. From 1989 to 1993, she was Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and from 1993 to 1995, Editor-In- Chief. From 2007 to 2015 she was Associate Editor of IEEE Transactions on VLSI Design of Circuits and Systems.

Award Recipients

2023Prof. Malgorzata Marek-Sadowska
2022Prof. Ricardo Augusto Da Luz Reis
2021Dr. Louis K. Scheffer (postponed from ISPD 2020)
2019Prof. Alberto Sangiovanni-Vincentelli
2018Prof. Te C. Hu
2017Prof. Satoshi Goto
2016Prof. Ralph Otten
2015Prof. Kurt Antreich
2014Dr. Bryan Preas
2013Prof. Yoji Kajitani
2012Prof. C.-L. Liu
2011Prof. Ernest Kuh

ISPD Best Paper Award

Since 2002, ISPD has recognized excellence by giving a best paper award.

Award Recipients

2022 Diwesh Pandey, Gustavo Tellez and James Leland, "LEO: Line End Optimizer for Sub-7nm Technology Nodes”
2021 Siddhartha Nath and Vishal Khandelwal, "Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes”
2020 W. Ye, M. Alawieh, Y. Watanabe, S. Nojima, Y. Lin, D. Pan, "TEMPO: Fast Mask Topography Effect Modeling with Deep Learning"
2019 N. Ryzhenko, S. Burns, A. Sorokin, M. Talalay, "Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints"
2018 C. Alpert, W. Chow, K. Han, A. Kahng, Z. Li, D. Liu, S. Venkatesh, "Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees"
2017 H. Zhang, F. Zhu, H. Li, E. Young, B. Yu, "Bilinear Lithography Hotspot Detection"
2016 W. Chang, L. Chen, C. Lin, S. Mu, M. Chao, C. Tsai, Y. Chiu, "Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique"
2015 H. Chien, S. Han, Y. Chen, T. Wang, "A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography"
2014 S. Roy, P. Mattheakis, L. Masse-Navette, D. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure"
2013 H. Xiang, M. Cho, H. Ren, M. Ziegler, R. Puri, "Network flow based datapath bit slicing"
2012 J. Yan, C. Chu, "Optimal Slack-Driven Block Shaping Algorithm in Fixed-Outline Floorplanning"
2011 K. Yuan, D. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters"
2010 L. Luo, T. Yan, Q. Ma, M. Wong, T. Shibuya, "B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing"
2009 Q. Liu, S. Sapatnekar, "Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction"
2008 S. Plaza, I. Markov, V. Bertacco, "Optimizing Non-Monotonic Interconnect Using Functional Simulation and Logic Restructuring"
2007 V. Khandelwal, A. Srivastava, "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation"
2006 J. Xiong, V. Zolotove, L. He, "Robust Extraction of Spatial Correlation"
2005 T. Chan, J. Cong, K. Sze, "Multilevel Generalized Force-Directed Method for Circuit Placement"
2004 N. Viswanathan, C. Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model"
2003 T. Wang, Y. Lee, C. Chen, "3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator"
2002 A. Rohe, U. Brenner, "An Effective Congestion Driven Placement Framework"