List of Accepted Papers

#5 Voltage-Drop Optimization Through Insertion of Extra Stripes To A Power Delivery Network
#6 Validating the Redundancy Assumption for HDL from Code Clone’s Perspective
#7 FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines
#10 Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits
#12 Pin Access-Oriented Concurrent Detailed Routing
#15 Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks
#16 Placement Initialization via Sequential Subspace Optimization with Sphere Constraints
#19 Security Closure of IC Layouts Against Hardware Trojans
#20 FastPass: Fast Pin Access Analysis with Incremental SAT Solving
#22 Combined Modeling of Electromigration, Thermal and Stress Migration in AC Interconnect Lines
#24 Pseudonym: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs
#26 X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks
#31 DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning