All times in Pacific Daylight Time (PDT = GMT-7). Central Europe (CEST) = PDT + 9. Taiwan/China = PDT + 15.
Across the three days for ISPD 2022, we had 6 keynotes, 12 accepted papers, 12 invited talks, two panels on Monday and Wednesday - each with 6 panelists, 3 speakers including Ricardo Reis with longer talks for his commemorative session, and finally the ISPD 2022 contest results.
Papers are accessible at this link.
Videos of the presentations are available at ISPD YouTube channel
6:00 - 8:00 pm PDT. Sunday Social Chit-Chat and Welcome on gather.town
Meet and greet cocktail hours with the general chairs of the organizing committee, Laleh Behjat (University of Calgary) and Stephen Yang (Leda Technology).
7:00 - 8:00 am PDT. Session 1 - Opening Session and First Keynote
Chairs: Laleh Behjat (University of Calgary) and Stephen Yang (Leda Technology) [Video]
"The Need for Speed: From Electric Supercars to Cloud Bursting for Design", Dean Drako (CEO of Eagle Eye Networks, IC Manage, and Drako Motors)
"Our industry has insatiable need for speed. In addition to fast products for consumer electronics, medical, mil-aero, security, smart sensors, AI processing, robots, and more, we also continuously push for higher performance for the processing and communication infrastructure needs for true hyper-connectivity. Dean Drako will compare our industry's drive for speed to electric supercars. He will then drill down into four key elements that advanced design and verification teams deploy to speed the delivery of their innovative products to successfully meet market windows."
8:00 - 8:15 am PDT. Break
8:15 - 9:00 am PDT. Session 2 - Placement, Clock Tree Synthesis, and Optimization
Chair: Deepashree Sengupta (Synopsys)
"In a typical RTL-to-GDSII flow, floorplanning plays an essential role in achieving decent quality of results (QoR). A good floorplan typically requires interaction between the frontend designer, who is responsible for the functionality of the RTL, and the backend physical design engineer. In this paper, we propose RTL-MP, a novel macro placer which utilizes RTL information and tries to “mimic” the interaction between the frontend RTL designer and the backend physical design engineer to produce human-quality floorplans. By exploiting the logical hierarchy and processing logical modules based on connection signatures ... "
2. "Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines", Chien-Pang Lu, Iris Hui-Ru Jiang and Chih-Wen Yang (National Taiwan University and DigWise Technology) [Slides] [Video]
"Bitcoin mining machines become a new driving force to push the physical limitation of semiconductor process technology. Instead of peak performance, mining machines pursue energy and computation efficiency of implementing cryptographic hash functions. Therefore, the state-of-the-art ASIC design of mining machines adopts near-threshold computing, deep pipelines, and unidirectional data flow. According to these design properties, in this paper, we propose a novel clock reversing tree design methodology for bitcoin mining machines. In the clock reversing tree, the clock of global tree is fed from the last pipeline stage backward to the first one ... "
3. "Kernel Mapping Techniques for Deep Learning Neural Network Accelerators", Sarp Ozdemir, Mohammad Khasawneh, Smriti Rao and Patrick H. Madden (State University of New York at Binghamton) [Slides] [Video]
"In this paper, we consider structural differences between deep learning neural networks and more conventional circuits - highlighting how this impacts strategies for mapping neural network compute kernels onto available hardware. We present an efficient mapping approach based on dynamic programming, and also a method to establish performance bounds. We also propose an architectural approach to extend the practical life time of hardware accelerators, enabling the integration of a variety of heterogenous processors into a high performance system. Experimental results using benchmarks from a recent ISPD contest are also reported."
9:00 - 9:15 am PDT. Break
9:15 - 10:15 am PDT. Session 3 - Design Flow Advances with Machine Learning and Lagrangian Relaxation
Chair: Ulf Schlichtmann (Technical University of Munich)
"Synthesis and place & route tools are highly leveraged for modern digital design. But, despite continuous improvement in CAD tool performance, products in competitive markets often set PPA (performance, power, area) targets beyond what the tools can natively deliver. These aggressive targets lead to circuit designers attempting to tune a vast number of design flow parameters in search of near-optimal design specific flow recipes. Compounding the complex design flow parameter tuning problem is that many digital design tools exhibit nondeterminism, i.e., run-to-run variation ... "
"Lagrangian relaxation (LR) based gate sizing is the state-of-the-art gate-sizing approach. We detail development of a LR gate sizer for an industrial P&R flow. Software architecture and P&R flow needs are discussed. We summarize how we sped up the LR sizer by 3x to resize a million gates per hour, and ensure multi-threaded results are deterministic. LR sizing experiments at the fast WNS/TNS optimization steps in the flow stages before and after clock tree synthesis (CTS) show excellent results: 10% to 20% setup timing total negative slack (TNS) reduction with 11% to 14% less leakage power, or 1% to 3% lower total power ... "
"Slowdown in process scaling is putting increasing pressure on EDA tools to bridge the power, performance and area (PPA) entitlement gap of Moore’s Law. State-of-the-art designs are pushing the PPA envelope to the limit, accompanied by increasing design size and complexity, and shrinking time-to-market constraints. In this talk we will discuss various challenges and opportunities in delivering best-in-class PPA closure with AI/ML augmented digital implementation tools. We will also talk about some aspects of large-scale industrial adoption of such a system and the AI capabilities needed to power these tools to minimize the need for an expert user ..."
"Engineering teams are always under pressure to deliver increasingly aggressive power, performance and area (PPA) goals, as fast as possible, on many concurrent projects. Chip designers often spend significant time tuning the implementation flow for each project to meet these goals. Cadence Cerebrus machine learning chip design flow optimization automates this whole process, delivering better PPA much more quickly. During this presentation Cadence will discuss Cerebrus machine learning and distributed computing techniques which enable RTL to GDS flow optimization, delivering better engineering productivity and design performance."
10:15 - 10:30 am PDT. Break
10:30 - 12:00 pm PDT. Session 4 - Panel on Traditional Algorithms Versus Machine Learning Approaches
Chair: Patrick Groeneveld (Cerebras Systems)
"The very first Design Automation Conference was held in 1964  when computers were programmed with punch cards. The initial topics were related to automated Printed Circuit Board design, cell placement, and early attempts at transient circuit analysis. The next decades saw the introduction of key graph algorithms and numerical analysis methods. Optimal algorithms and more practical heuristic methods were published. The 1980ies saw the advent of simulated annealing, a universal heuristic optimization method that found many applications. The next decade introduced powerful numerical placement methods for millions of cells ... "
"The application of machine learning (ML) in EDA is a hot research trend. To use ML in EDA, it is nature to think from the ML method point of view, i.e. supervised learning, reinforcement learning and unsupervised learning. Based on this point of view, we can roughly classify the ML applications in EDA into three categories: prediction, optimization, and generation."
3. "How Vertical ML Platforms Echo EDA Design Flows", Igor Markov (University of Michigan and Meta) [Slides] [Video]
"For years, integrated circuit design has been a driver for algorithmic advances. The problems encountered in the design of modern circuits are often intractable - and with exponentially increasing size. In this paper, we argue that there are multiple forces which have prevented full automation - and a lack of algorithmic methods is not the only factor. If the time has come for automation, there are a number of “traditional” methods that should be considered again. We focus on recursive bisection, and highlight key ideas from partitioning algorithms that have broader impact than one might expect ... "
5. "An Open-Source Deep Reinforcement Learning Framework for Chip Placement", Summer Yue, Ebrahim M. Songhori, Joe Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini and Sergio Guadarrama (Google Research) [Slides] [Video]
"Chip floorplanning is a complex task within the physical design process In a recent paper published in Nature , a new methodology based on deep reinforcement learning was proposed that solves the floorplanning problem for advanced chip technologies with production quality results. In this paper, we describe Circuit Training , an open-source distributed reinforcement learning framework that re-implements the proposed methodology in TensorFlow v2.x. We will explain the framework and discuss ways it can be extended to solve other important problems within physical design and more generally chip design ... "
12:00 - 12:10 am PDT. Break
12:10 - 1:00 pm PDT. Session 5 - Second Keynote
Chair: Louis K. Scheffer (Howard Hughes Medical Institute)
"The Cerebras CS-2: Designing an AI Accelerator Around the World's Largest 2.6 Trillion Transistor Chip", Jean-Philippe Fricker (Chief System Architect at Cerebras Systems)
"The computing and memory demands from state-of-the-art neural networks have increased several orders of magnitude in just the last couple of years, and there's no end in sight. In this talk, Cerebras Co-Founder and Chief Systems Architect Jean-Philippe Fricker will explore the fundamental properties of neural networks and why they are not well served by traditional architectures. He will examine how co-design can relax the traditional boundaries between technologies and enable designs specialized for neural networks with new architectural capabilities and performance ..."
1:00 - 1:30 pm PDT. Chit-Chat on Gather.Town
7:00 - 7:50 am PDT. Session 6 - Third Keynote
Chair: Chuck Alpert (Cadence Design Systems)
"Since June 2018, the OpenROAD project has developed an opensource, RTL-to-GDS EDA system within the DARPA IDEA program. The tool achieves no-human-in-loop generation of design rule clean layout in 24 hours. Since November 2021, The Institute for Learning-enabled Optimization at Scale (TILOS), an NSF AI institute for advances in optimization partially supported by Intel, has begun its work toward a "new nexus" of AI, optimization, and the leading edge of practice for use domains that include IC design. This paper traces a trajectory of "leveling up" in the research enablement for IC physical design automation and EDA in general ... "
7:50 - 8:00 am PDT. Break
8:00 - 8:45 am PDT. Session 7 - Prototyping, Packaging, and Integration
Chair: Tiago Reimann (Siemens EDA)
"Technology scaling has enabled the semiconductor industry to successfully address the application performance demands. This talk will outline the promise of the 3D system-of-chips design and present key design and verification challenges faced by the engineering teams associated with the development of such systems. It will discuss how a holistic design solution consisting of end-to-end design automation, integrated tools, die-to-die IP and methodologies can provide unique benefits in system-level design flow optimization and pave the way to achieving optimal power, performance and transistor volume density ..."
2. "Novel Methodology for Assessing Chip-Package Interaction Effects on Chip Performance", Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Massimo Bertoletti, Carmelo Maiorca, Rossana Zadra, Massimo Inzaghi, Gabriele Gattere, Giancarlo Zinco, Paolo Valente, Roberto Bardelli, Alessandro Valerio, Pierluigi Rolandi, Mattia Monetti, Valentina Cuomo and Salvatore Santapa (Siemens EDA and STMicroelectronics) [Slides] [Video]
"The paper presents a multiscale simulation methodology and EDA tool that assesses the effect of thermal mechanical stresses arising after die assembly on chip performance. Existing non uniformities of feature geometries and composite nature of on-chip interconnect layers are addressed by developed methodology of the anisotropic effective thermomechanical material properties (EMP) that reduces complexity of FEA simulations and enhances the accuracy and performance. Physical nature of the calculated EMP makes it scalable with the simulation grid size, enabling resolution of stress/strain at different scales from package to device channel ... "
3. "On Ensuring Congruency with Implementation During Emulation and Prototyping", Alex Rabinovitch (Synopsys) [Video]
"ASIC-style design implementation ensures a certain degree of determinism in design behavior when it comes to glitches in clock cones and hold violations. Those techniques are surveyed and shown to be inherently rooted in modelling the timeline in a manner that creates an artificial common source of synchronization between different clocks in design. Also the capability of low skew clock lines provided by FPGA vendors is leveraged. However, this overall approach could result in performance degradation and techniques are presented to compensate for the degradation. "
8:45 - 9:00 am PDT. Break
9:00 - 10:00 am PDT. Session 8 - 3D IC Design
Chair: Lang Feng (Nanjing University)
"3D ICs have increasingly become popular as they provide a way to pack more functionality on a chip and reduce manufacturing cost. TSMC offers a number of packaging technologies under the umbrella of “3D Fabric” to suit different product requirements. Just like any new technology, 3D Fabric brings forward several challenges associated with system, design, thermal as well as testing that require effective and efficient solutions before 3D Fabric can be used in high volume production. In this presentation, we will give a brief introduction about various 3D Fabric offerings and discuss challenges from a semiconductor foundry perspective. "
2. "Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration", Tanay Karnik (Intel) [Video]
"In this presentation, we will review the recent advances in chiplet-based commercial products and prototypes [2,3,4,5]. Most chiplet usage has been confined to integrating die designed by the same organization applied to building chips for the same product types. The right approach should be able to reduce portfolio costs, scale innovation and improve time to solution . It is important to manage the associated trade-offs, such as thermal, power, I/O escapes, assembly, test, etc. We will conclude the talk by presenting the future 2.xD/3D integration opportunities becoming available . "
3. "ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs", Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo and Sung Kyu Lim (Georgia Institute of Technology and Peking University) [Slides] [Video]
"In this paper,we showthat true 3D placement approaches, enhanced with reinforcement learning, can offer further PPA improvements over pseudo-3D approaches. To accomplish this goal, we integrate an academic true 3D placement engine into a commercial-grade 3D physical design flow, creating ART-3D flow (Analytical 3D Placement with Reinforced Parameter Tuning-based 3D flow). We use a reinforcement learning (RL) framework to find optimized placement parameter setting of the true 3D placement engine for a given netlist and perform high-quality 3D placement. We then use an efficient 3D optimization and routing engine ..."
4. "Intelligent Design Automation for Heterogeneous Integration", Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang and Charlie Chung-Ping Chen (National Taiwan University) [Video]
"As the design complexity grows dramatically in modern circuit designs, 2.5D/3D heterogeneous integration (HI) becomes effective for system performance, power, and cost optimization, providing promising solutions to the increasing cost of more-Moore scaling. In this talk, we investigate the chip, package, and board co-design methodology with advanced packages and optical communication considering essential issues on physical design, electrical, thermal, and mechanical effects, timing, and testing, and suggest future research opportunities: layout, timing, testing, integration ..."
10:00 - 10:15 am PDT. Break
10:15 - 11:00 am PDT. Session 9 - Routing
Chair: Jhih-Rong Gao (Flex Logix Technologies)
1. "A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction", Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li and Mango C.-T. Chao (National Yang Ming Chiao Tung University and Realtek) [Slides] [Video]
"This paper presents a router, which tackles a classic algorithm problem in EDA, obstacle-avoiding rectilinear Steiner minimum tree (OARSMT), with the help of an agent trained by our proposed policy-based reinforcement-learning (RL) framework. The job of the policy agent is to select an optimal set of Steiner points a given layout. Our RL framework can iteratively upgrade the policy agent by applying Monte-Carlo tree search to explore and evaluate various choices of Steiner points on various unseen layouts. As a result, our policy agent can be viewed as a self-designed OARSMT algorithm that can iteratively evolves by itself ..."
"Sub-7nm technology nodes have introduced new challenges, specifically in the lower metal layers. Extreme Ultraviolet Lithography (EUV) and multi-patterning-based lithography such as Self-Aligned Double Patterning (SADP) solutions have become key choices for the manufacturing of these layers. The demand for microprocessors has increased tremendously in the last few years and this imposes another challenge to the chip manufacturers to build their products at a very rapid rate. These days a mix of different lithography solutions for the manufacturing of metal layers is quite common ..."
"A 3D Integrated Circuit consists of two or more dies bonded to each other in the vertical direction. This allows for a high transistor density without a need for shrinking the underlying transistor dimensions. While it has been shown to improve design power, performance, and area (PPA) due to the stacked Front End Of the Line (FEOL) layers, the Back End Of the Line (BEOL) structure of the stacked IC also allows for novel routing scenarios. With the split dies in 3D, nets would need to connect cells from different tiers, across many vertical layers and multiple FEOLs. Nets connecting cells in a single tier could still use metal layers from the BEOL of other tiers ... "
11:00 - 11:10 am PDT. Break
11:10 - 12:00 pm PDT. Session 10 - Fourth Keynote
Chair: Jens Lienig (Dresden University of Technology)
"Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era", Aiqun Cao (VP of Engineering for Digital Implementation at Synopsys)
"The SysMoore Era can be characterized as the widening gap between classic Moore's Law scaling and increasing system complexity. System-on-a-chip complexity has now fallen by the wayside to systems-of-chips with the need for smaller process nodes, and multi-die integration. With engineers handling not just larger chip designs but systems of multiple chips, the focus on user productivity and design robustness becomes a major factor getting designs to market in the fastest time and with the best possible PPA. Combining a hyperconvergent design flow with smart data analytics and AI-based solution space exploration provides a huge benefit ..."
12:00 - 12:15 pm PDT. Break
12:15 - 1:30 pm PDT. Session 11 - Lifetime Achievement Commemoration for Ricardo Reis [Biography] [Video]
Chair: Jose Luiz Guntzel (Federal University of Santa Catarina)
"Quantum electronic circuits where the logic information is processed and stored in single flux quanta promise efficient computation in a performance/power metric, and thus are of utmost interest as possible replacement or enhancement of CMOS. Several electronic device families leverage superconducting materials and transitions between resistive and superconducting states. Information is coded into bits with deterministic values - as opposed to qubits used in quantum computing. As an example, information can be coded into pulses. Logic gates can be modeled as finite-state machines, that emit logic outputs in response to inputs ... "
"This talk offers a review of possibilities to explore on VLSI layout beyond traditional standard cell methodology. Existing Physical Design tools strictly avoid any modification to the contents of Standard Cells. Here, a post-processing step based on SAT solvers is proposed to obtain optimal solutions for local transistor level layout synthesis problems. This procedure can be constrained by metrics that ensure that quality is not degraded, and an acceptable and better-quality timing model can be rebuilt for the block. These problems and techniques are open research opportunities in Physical Design ..."
"By end of years 70's, microprocessors were designed by hand showing an excellent layout compaction. It will be shown some highlights of the reverse engineering of the Z8000 which control part was designed by hand, showing several layout optimization strategies. The observation of the Z8000 layout inspired the research of methods to do the automatic generation of the layout of any transistor network, allowing to reduce the number of transistors to implement a circuit, and by consequence the leakage power. Some of the layout automation tools developed by our group is briefly presented."
1:30 - 2:00 pm PDT. Chit-Chat on Gather.Town with Ricardo Reis
7:00 - 7:50 am PDT. Session 12 - Fifth Keynote
Chair: Bei Yu (Chinese University of Hong Kong)
"The last few years have seen an accelerating growth in the demand for new silicon designs, even as the size and complexity of those designs has increased. However, the gains in design productivity necessary to implement these designs efficiently have not kept up. We need more than an order of magnitude increase in design productivity by the end of the decade to keep up with demand. Traditional methods for improving physical design tool capabilities are running out of steam, and there is a strong need for new approaches. Over the last two decades, we have seen other areas of computer science such as computer vision, speech recognition ..."
7:50 - 8:00 am PDT. Break
8:00 - 9:00 am PDT. Session 13 - Advances in Analog and Full Custom Design Automation
Chair: Mark Po-Hung Lin (National Yang Ming Chiao Tung University)
"The vast majority of state-of-the-art integrated circuits are mixed-signal chips. While the design of the digital parts of the ICs is highly automated, the design of the analog circuitry is largely done manually; it is very time-consuming; and prone to error. Among the reasons generally listed for this is often the attitude of the analog designer. The fact is that many analog designers are convinced that human experience and intuition are needed for good analog design. This is why they distrust the automated synthesis tools. This observation is quite correct, but this is only a symptom of the real problem ..."
2. "Analog/Mixed-Signal Layout Optimization using Optimal Well Taps", Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns and Sachin S. Sapatnekar (University of Minnesota and Intel) - best paper nominee [Slides] [Video]
"Well island generation and well tap placement pose an important challenge in automated analog/mixed-signal (AMS) layout. Well taps prevent latchup within a radius of influence in a well island, and must cover all devices. Automated AMS layout flows typically performwell island generation and tap insertion as a postprocessing step after placement. However, this step is intrusive and potentially alters the placement, resulting in increased area, wire length, and performance degradation. This work develops a graph-based optimization that integrates well island generation, well tap insertion, and placement ..."
"While the majority of research in design automation for analog circuits has been relying on statistical solution approaches, deterministic approaches are an attractive alternative. This paper gives a few examples of deterministic methods for sizing, structural synthesis and layout synthesis of analog circuits, which have been developed over the past decades. It starts from the socalled characteristic boundary curve for interactive parameter optimization, and ends at recent approaches for structural synthesis of operational amplifiers based on functional block composition ..."
4. "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies", Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan and Haoxing Ren (University of Texas at Austin and NVIDIA) [Slides] [Video]
"Despite continuous efforts in layout automation for full-custom circuits, including analog/mixed-signal (AMS) designs, automated layout tools have not yet been widely adopted in current industrial full-custom design flows due to the high circuit complexity and sensitivity to layout parasitics. Nevertheless, the strict design rules and grid-based restrictions in nanometer-scale FinFET nodes limit the degree of freedom in full-custom layout design and thus reduce the gap between automation tools and human experts. This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. "
9:00 - 9:15 am PDT. Break
9:15 - 10:45 am PDT. Session 14 - Panel on Challenges and Approaches in VLSI Routing [Video]
"In this session, we will first have a brief review of the ISPD 2018 and 2019 Initial Detailed Routing Contests. We will then visit a few important and interesting topics in VLSI routing that includes GPU accelerated routing, signal speed optimization in routing, PCB routing and AI-driven analog routing."
Chair: Gracieli Posser (Cadence Design Systems)
1. "Complex routing design rules and the ISPD 2018/2019 Initial Detailed Routing Contests", Gracieli Posser (Cadence Design Systems) [Slides] [Video]
2. "GPU Accelerated Routing", Evangeline F.Y. Young (Chinese University of Hong Kong) [Slides] [Video]
3. "Signal Speed Optimization in Routing", Stephan Held (University of Bonn) [Slides] [Video]
"Package routing is typically done by semi-auto or manual manners in order to meet several customized requests for different design styles. However, in recent years, the scale of package designs rapidly enlarges, and routing rules become more and more complicated, such that the engineering effort of the manual solution increases dramatically. Therefore, the need of full-auto solution becomes necessary and critical. In addition, in order to build an automatic design flow for 3D-IC, full-auto package routing is one of most important pieces. There are many challenges for realizing full-auto package routing solution. Paper is listing some of the challenges."
5. "Integrating Human and Machine Intelligence into Analog Routing", David Z. Pan (University of Texas at Austin) [Slides] [Video]
6. "Printed Circuit Board (PCB) Routing", Yih-Lang Li (National Yang Ming Chiao Tung University) [Slides] [Video]
10:45 - 11:00 am PDT. Break
11:00 - 11:45 am PDT. Session 15 - Global Placement, Macro Placement, and Legalization
Chair: Joseph Shinnerl (Siemens EDA)
1. "Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-Design Model Applicability and the Discerning Ensemble", Xiang Gao, Pedja Raspopovic, Vineet Rashingkar, Yi-Min Jiang, Menno E. Verbeek, Amit Jalota, Lixin Shao and Manish Sharma (Synopsys) [Slides] [Video]
"Modern very large-scale integration (VLSI) designs typically use a lot of macros (RAM, ROM, IP) that occupy a large portion of the core area. Also, macro placement being an early stage of the physical design flow, followed by standard cell placement, physical synthesis (place-opt), clock tree synthesis and routing, etc., has a big impact on the final quality of result (QoR). There is a need for Electronic Design Automation (EDA) physical design tools to provide predictions for congestion, timing, and power etc., with certainty for different macro placements before running time-consuming flows ..."
"Cell placement is such a critical step for chip physical design that it needs many kinds of efforts for improvement. Recently, designs with 2D processing element arrays have become popular primarily due to their deep neural network computing applications. The 2D array regularity is similar to but different from the regularity of conventional datapath designs. To exploit the 2D array regularity, this work develops a new global placement technique built upon RePlAce. Experimental results show that the proposed technique can reduce half-perimeter wirelength and Steiner tree wirelength by about 6% and 12%."
3. "Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement", Chung-Hsien Wu, Wai-Kei Mak and Chris Chu (National Tsing Hua University and Iowa State University) [Slides] [Video]
"Due to the aggressive scaling of advanced technology nodes, multiple-row-height cells have become more and more common in VLSI design. Consequently, the placement of cells is no longer independent among different rows, which makes the traditional row-based legalization techniques obsolete. In this work, we present a highly efficient linear-time mixed-cell-height legalization approach that optimizes both the total cell displacement and the maximum cell displacement. First, a fast window-based cell insertion technique introduced in  is applied to obtain a feasible initial row assignment and cell ordering ..."
11:45 - 11:50 pm PDT. Break
11:50 - 12:50 pm PDT. Session 16 - Sixth Keynote
Chair: Ajay Joshi (Boston University)
"Hardware Security: Physical Design Versus Side-Channel and Fault Attacks", Ingrid Verbauwhede (Professor at Katholieke Universiteit Leuven and at the University of California at Los Angeles)
"What is "hardware" security? How can we improve trustworthiness in hardware circuits? Is there a design method for secure hardware design? To answer these questions, different communities have different expectations of trusted (expecting trustworthy) hardware components upon which they start to build a secure system. At the same time, electronics shrink: sensor nodes, IOT devices, smart electronics are becoming more and more available. In the past, adding security was only a concern for locked server rooms or now cloud servers. However, these days, our portable devices contain highly private and secure information. ..."
12:50 - 1:00 pm PDT. Break
1:00 - 2:00 pm PDT. Session 17 - ISPD 2022 Contest Results and Closing Remarks
Chair: David Chinnery (Siemens EDA)
"Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest", Johann Knechtel, Jayanth Gopinath, Mohammed Ashraf, Jitendra Bhandari, Ozgur Sinanoglu and Ramesh Karri (New York University) [Slides]
"Computer-aided design (CAD) tools mainly optimize for power, performance, and area (PPA). However, given a large number of serious hardware-security threats that are emerging, future CAD flows must also incorporate techniques for designing secure integrated circuits (ICs). In fact, the stakes are quite high for IC vendors and design companies, as security risks that are not addressed during design time will inevitably be exploited in the field, where vulnerabilities are almost impossible to fix. However, there is currently little to no experience related to designing secure ICs available within the CAD community ..."
"Closing remarks and outlook to ISPD 2023", David Chinnery (ISPD 2023 General Chair) [Slides] [Video]
2:00 - 2:30 pm PDT. Farewell Chit-Chat on Gather.Town.