March 27-30, 2022 Banff, Alberta, Canada,
and virtual participation across the world
ISPD 2022 Accepted Papers
| 5 | Chien-Pang Lu, Iris Hui-Ru Jiang and Chih-Wen Yang Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines |
| 9 | Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li and Mango C.-T. Chao A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction |
| 13 | Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno Verbeek, Manish Sharma, Vineet Rashingkar and Amit Jalota Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble |
| 15 | Donghao Fang, Boyang Zhang, Hailiang Hu, Wuxi Li, Bo Yuan and Jiang Hu Global Placement Exploiting Soft 2D Regularity |
| 19 | Chung-Hsien Wu, Wai-Kei Mak and Chris Chu Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement |
| 24 | Gauthaman Murali, Sandra Maria Shaji, Anthony Agnesina, Guojie Luo and Sung Kyu Lim ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs |
| 25* | Diwesh Pandey, Gustavo Tellez and James Leland LEO: Line end optimizer for sub-7nm technology nodes |
| 28 | Matthew Ziegler, Lakshmi Reddy and Robert Franch Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning |
| 29* | Ramprasath S, Arvind Kumar Sharma, Meghna Madhusudan, Soner Yaldiz, Jitesh Poojary, Ramesh Harjani, Steven M. Burns and Sachin S. Sapatnekar Analog/Mixed-Signal Layout Optimization using Optimal Well Taps |
| 30 | Sai Pentapati and Sung Kyu Lim Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs |
| 32 | Sarp Ozdemir, Mohammad Khasawneh, Smriti Rao and Patrick Madden Kernel Mapping Techniques for Deep Learning Neural Network Accelerators |
| 35 | Andrew B. Kahng, Ravi Varadarajan and Zhiang Wang RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement |
*Best paper candidates.