March 27-30, 2022
Virtual only participation

ISPD Lifetime Achievement Award

This award is given to individuals who have made outstanding contributions to the field of physical design automation over multiple decades. The purpose is to recognize their lifetime of achievements and contributions in terms of research work, education, and professional service.

The 2022 International Symposium on Physical Design paid tribute to Prof. Ricardo Reis for his instrumental impact on EDA research in South America and contributions to the physical design community.

Professor Ricardo Reis had a short introduction to Microelectronics in his EE at UFRGS (Universidade Federal do Rio Grande do Sul), in Brazil. Then, he went to INPG, France, to do a PhD, but before starting the PhD he did the reverse engineering of the Z8000 microprocessor, that was a great experience to learn many issues that were not in books or papers. The PhD was related to floorplanning.

After finishing his PhD, he returned to UFRGS, where he was a founder of the UFRGS Microelectronics Group. The experience with reverse engineering of the Z8000 inspired the beginning of research in layout design automation. One of the first research works was related to the development of a cell-based layout design automation tool with connections over the cells, avoiding the standard cell approach used that time, using routing channels between cell rows. Since then, Ricardo has advised more than 100 graduate students, those are working in Brazil and in several countries around the world. Several teams with UFRGS students won some EDA Contests like ISPD and ICCAD ones. One of his main research projects is still related to layout design automation of any transistor network. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings.

He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award in 2011, 2012, and 2018, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He was also the founder of the IEEE CEDA Chapter. He is a founder of several conferences and events like SBCCI, LASCAS, SERESSA, EMicro. Those conferences bring knowledge and research opportunities to Brazil and Latin America.

Professor Reis was the General and Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was a member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. In 2021, Ricardo received the IFIP Fellow Award.

Award Recipients

2022Prof. Ricardo Augusto Da Luz Reis
2021Dr. Louis K. Scheffer (postponed from ISPD 2020)
2019Prof. Alberto Sangiovanni-Vincentelli
2018Prof. Te C. Hu
2017Prof. Satoshi Goto
2016Prof. Ralph Otten
2015Prof. Kurt Antreich
2014Dr. Bryan Preas
2013Prof. Yoji Kajitani
2012Prof. C.-L. Liu
2011Prof. Ernest Kuh

ISPD Best Paper Award

Since 2002, ISPD has recognized excellence by giving a best paper award.

Award Recipients

2022 Diwesh Pandey, Gustavo Tellez and James Leland, "LEO: Line End Optimizer for Sub-7nm Technology Nodes”
2021 Siddhartha Nath and Vishal Khandelwal, "Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes”
2020 W. Ye, M. Alawieh, Y. Watanabe, S. Nojima, Y. Lin, D. Pan, "TEMPO: Fast Mask Topography Effect Modeling with Deep Learning"
2019 N. Ryzhenko, S. Burns, A. Sorokin, M. Talalay, "Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints"
2018 C. Alpert, W. Chow, K. Han, A. Kahng, Z. Li, D. Liu, S. Venkatesh, "Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees"
2017 H. Zhang, F. Zhu, H. Li, E. Young, B. Yu, "Bilinear Lithography Hotspot Detection"
2016 W. Chang, L. Chen, C. Lin, S. Mu, M. Chao, C. Tsai, Y. Chiu, "Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique"
2015 H. Chien, S. Han, Y. Chen, T. Wang, "A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography"
2014 S. Roy, P. Mattheakis, L. Masse-Navette, D. Pan, "Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure"
2013 H. Xiang, M. Cho, H. Ren, M. Ziegler, R. Puri, "Network flow based datapath bit slicing"
2012 J. Yan, C. Chu, "Optimal Slack-Driven Block Shaping Algorithm in Fixed-Outline Floorplanning"
2011 K. Yuan, D. Pan, "E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters"
2010 L. Luo, T. Yan, Q. Ma, M. Wong, T. Shibuya, "B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing"
2009 Q. Liu, S. Sapatnekar, "Synthesizing a Representative Critical Path for Post-Silicon Delay Prediction"
2008 S. Plaza, I. Markov, V. Bertacco, "Optimizing Non-Monotonic Interconnect Using Functional Simulation and Logic Restructuring"
2007 V. Khandelwal, A. Srivastava, "Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation"
2006 J. Xiong, V. Zolotove, L. He, "Robust Extraction of Spatial Correlation"
2005 T. Chan, J. Cong, K. Sze, "Multilevel Generalized Force-Directed Method for Circuit Placement"
2004 N. Viswanathan, C. Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model"
2003 T. Wang, Y. Lee, C. Chen, "3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator"
2002 A. Rohe, U. Brenner, "An Effective Congestion Driven Placement Framework"