Symposium Program

A printable version (PDF) of the technical program can be downloaded here.

Sunday, April 14

5:30pm - 7:00pm: Reception at the Mezzanine in the Sir Francis Drake Hotel

Monday, April 15

7:45am - 8:45am: Breakfast

8:45am - 9:00am: General Chair Welcome Message

9:00am - 10:00am: Keynote

Session Chair: Ismail Bustany (Xilinx, Inc.)

“Fusion: The Dawn of the Hyperconvergence Era in EDA”, Shankar Krishnamoorthy (Synopsys, Inc.), (Invited)

10:00am - 10:30am: Morning Break

10:30am - 12:30pm: New Advances in Placement

Session Chair: Stephen Yang (Xilinx, Inc.)

“How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization”, Renan Netto, Sheiny Fabre, Tiago Augusto Fontana (Federal University of Santa Catarina), Vinicius Livramento (ASML), Laércio Pilla (Université Paris-Sud), José Luís Güntzel (Federal University of Santa Catarina) (Best Paper Award candidate) [Slides].

“Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing”, Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang (National Taiwan University), Gi-Joon Nam (IBM Research) [Slides]

“Device Layer-Aware Analytical Placement for Analog Circuits”, Biying Xu, Shaolan Li (University of Texas at Asutin), Chak-Wa Pui (The Chinese University of Hong Kong), Derong Liu (Cadence Design Systems), Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan (University of Texas at Austin) (Best Paper Award candidate) [Slides]

“Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization”, Xingquan Li (Minnan Normal University), Jianli Chen, Wenxing Zhu (Fuzhou University), Yao-Wen Chang (National Taiwan University) [Slides]

12:30pm - 2:00pm: Lunch

2:00pm - 3:30pm: FPGA Special Session: Advances in Adaptable Heterogeneous Computing and Acceleration for Big Data

Session Chair: Mahesh Iyer (Intel Corporation)

“FPGA-based Computing in the Era of AI and Big Data”, Eriko Nurvitadhi (Intel Corporation), (Invited)


“Advances in Adaptable Computing”, Amit Gupta (Xilinx, Inc.), (Invited) [Slides]

“Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms”, Muhammet Mustafa Ozdal (Bilkent University), (Invited)

3:30pm - 4:00pm: Afternoon Break

4:00pm - 6:00pm: Routing in All Forms

Session Chair: Patrick Madden (SUNY Binghamton)

“Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints”, Nikolay Ryzhenko, Steven Burns, Anton Sorokin, Mikhail Talalay (Intel Corporation) (Best Paper Award candidate) [Slides]

“PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs", ONoCs”, Alexandre Truppel (Faculdade de Engenharia, Universidade do Porto), Tsun-Ming Tseng (Chair of Electronic Design Automation, TUM), Davide Bertozzi (University of Ferrara), José Carlos Alves (Faculdade de Engenharia, Universidade do Porto), Ulf Schlichtmann (Chair of Electronic Design Automation, TUM) [Slides]

“Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing”, Sheng-En David Lin, Dae Hyun Kim (Washington State University) [Slides]

“ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques”, Dongwon Park (University of California, San Diego), Ilgweon Kang (Cadence Design Systems), Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng (University of California, San Diego) [Slides]

7:00pm - 9:00pm: Dinner/Social Event

Tuesday, April 16

7:45am - 8:45am: Breakfast

9:00am - 10:00am: Keynote

Session Chair: Noel Menezes (Intel Corporation)

“A Perspective on Security and Trust Requirements for the Future”, Kenneth Plaks (DARPA), (Invited) [Slides]

10:00am - 10:30am: Morning Break

10:30am - 12:30pm: Patterning and Machine Learning

Session Chair: Evangeline Young (The Chinese University of Hong Kong)

“Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling”, Gyuszi Suto, Geoff S. Greenleaf, Phanindra Bhagavatula, Heinrich R. Fischer, Sanjay K. Soni, Brian H. Miller, Renato F. Hentschke (Intel Corporation) [Slides]

“Electromigration-Aware Interconnect Design”, Sachin S. Sapatnekar (University of Minnesota), (Invited) [Slides]

“Toward Intelligent Physical Design: Deep Learning and GPU Acceleration”, Haoxing Ren (Nvidia Corporation), (Invited)

“Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement”, Hua-Yu Chang (Synopsys, Inc.), Iris Hui-Ru Jiang (National Taiwan University) [Slides]

12:30pm - 2:00pm: Lunch

2:00pm - 3:30pm: Cyber-Physical Systems

Session Chair: Patrick Groeneveld (Cadence Design Systems)

“From Electronic Design Automation to Automotive Design Automation”, Chung-Wei Lin (National Taiwan University), (Invited)

“Enterprise-wide AI-enabled Digital Transformation”, Mehdi Maasoumy (C3, Inc.), (Invited) [Slides]

“Secure and Trustworthy Cyber-Physical System Design: A Cross-Layer Perspective”, Pierluigi Nuzzo (University of Southern California), (Invited) [Slides]

3:30pm - 4:00pm: Afternoon Break

4:00pm - 6:00pm: Lifetime Achievement Award Tribute to Professor Alberto Sangiovanni-Vicentelli

Session Chair: Pierluigi Nuzzo (University of Southern California)

“The Slow Start of Fast Spice: A Brief History of Timing”, Jacob K. White (Massachusetts Institute of Technology), (Invited) [Slides]

“Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions”, Masahiro Fujita (University of Tokyo), (Invited) [Slides]

“From Electronic Design Automation to Cyber-Physical System Design Automation: A Tale of Platforms and Contracts”, Pierluigi Nuzzo (University of Southern California), (Invited)

“My 50-Year Journey from Punched Cards to Swarm Systems”, Alberto Sangiovanni Vincentelli (University of California, Berkeley), (Invited)

6:30pm - 9:00pm: Lifetime Achievement Award Dinner Banquet Keynote

7:00pm - 7:30pm: Keynote: "Freedom From Choice and the Power of Models: In Honor of Alberto Sangiovanni-Vincentelli", Edward A. Lee (University of California, Berkeley)

Wednesday, April 17

7:45am - 8:45am: Breakfast

8:45am - 10:15am: Physical Design - Where are we going?

Session Chair: C.K. Cheng (University of California, San Diego)

“Analog Layout Synthesis: Are We There Yet?”, Prasanth Mangalagiri (Intel Corporation), (Invited)

“Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach”, Ankur Sharma, David Chinnery (Mentor Graphics), Chris Chu (Iowa State University) [Slides]

“Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis”, Xiao Shi (Fudan University & University of California, Los Angeles), Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi (Southeast University), Lei He (Fudan University & University of California, Los Angeles) [Slides]

10:15am - 10:30pm: Morning Break

10:30am - 12:00pm: Detailed Routing Contest Results

Session Chair: David Chinnery (Mentor Graphics)

“ISPD 2019 Initial Detailed Routing Contest and Benchmarks with Advanced Routing Rules”, Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser (Cadence Design Systems)

12:00pm - 1:00pm: Lunch

1:00pm - 1:45pm: Poster Session

2:00pm - 3:30pm: Special Panel on ML in Physical Design: Opportunities, Infrastructure, and Deployment

Session Chair: Ismail Bustany (Xilinx, Inc.)

Panelists: Laleh Behjat, (University of Calgary); Ivan Kissiov, (Mentor Graphics); Harold Levy, (Synopsys, Inc); Ashish Sirasao, (Xilinx, Inc.); Haoxing Ren, (Nvidia Corporation); Venkat Thanvantri, (Cadence Design Systems)

3:45pm - 6:00pm: Urban hike social event.