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2016 International Symposium on Physical Design
With a Tribute to Prof. Ralph Otten
Santa Rosa, California, April 3-6, 2016


The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI, biological or other advanced technology systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing.

Regular presentations are 30 minutes.

SUNDAY, April 3

5:30 – 7:00 pm: Reception

MONDAY, April 4

8:45 – 10:00 am: Welcome and Keynote Address

Host: Evangeline Young (Chinese University of Hong Kong)

Monday Keynote: "Circuit Design in Nano-Scale CMOS Technologies", Kevin Zhang (Intel)

10:00 – 10:30 am: Morning Break

10:30 am – 12:30 pm Session 1: 3D Circuits

Session Chair: David Chinnery (Mentor Graphics)

(Invited) “Physical Design Automation for 3D Chip Stacks -- Challenges and Solutions”, Johann Knechtel (Masdar Institute of Science and Technology), Jens Lienig (Dresden University of Technology) [slides]

“ePlace-3D: Electrostatics based Placement for 3D-ICs”, Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen and Chung-Kuan Cheng. [slides]

“A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data”, Hantao Huang, Hao Yu, Cheng Zhuo and Fengbo Ren. [slides]

“PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip”, Anja von Beuningen and Ulf Schlichtmann. [slides]

12:30 – 2:00 pm: Lunch

Host: Qi Zhu (University of California, Riverside)

(Invited) “Optimizing for Power, Speed, Cost and Emissions in Automotive Drivetrains”, Patrick Groeneveld (Synopsys)

2:00 – 3:30 pm Session 2: Directed Self Assembly

Session Chair: Dwight Hill (Synopsys)

(Invited) “Cell-Based Design Methods for Directed Self-Assembly ”, Karl Berggren, Caroline A. Ross, Hyung Wan Do, Jae-Byum Chang, Hong Kyoon Choi (MIT) [slides]

“Concurrent Guiding Template Assignment and Redundant Via Insertion for DSA-MP Hybrid Lithography”, Jiaojiao Ou, Bei Yu and David Z. Pan. [slides]

“Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs”, Zhi-Wen Lin and Yao-Wen Chang. [slides]

3:30 – 4:00 pm: Afternoon Break

4:00 – 5:30 pm Session 3: Special Session

Session Chair: Mahesh A. Iyer (Intel Corporation)

(Invited) “Technology Inflection Points”, Victor Moroz (Synopsys) [slides]

(Invited) “Challenges and Opportunities with Place and Route of Modern FPGA Designs”, Raymond Nijssen (Achronix)

(Invited) “Design and Tool Flow of IBM's TrueNorth: An Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons”, Filipp Akopyan (IBM)

6:15 – 8:00 pm: Dinner Banquet

TUESDAY, April 5

9:00 – 10:00 am: Tuesday Keynote Address

Host: Yao-Wen Chang (National Taiwan University)

Tuesday Keynote: “Some Observations on the Physical Design of the Next Decade”, Antun Domic (Synopsys)

10:00 – 10:30 am: Morning Break

10:30 am – 12:30 pm Session 4: Timing and Clock Optimization

Session Chair: Gustavo Wilke (Synopsys)

(Invited) “A Designer’s Perspective on Timing Closure”, Greg Ford (Global Foundries) [slides]

“Cell Selection for High-Performance Designs in an Industrial Design Flow”, Tiago J. Reimann, Cliff C. N. Sze and Ricardo Reis. [slides]

“Drive Strength Aware Cell Movement Techniques for Timing Driven Placement”, Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo Johann and Ricardo Reis. [slides]

“Construction of Latency-Bounded Clock Trees”, Rickard Ewetz, Chuan Yean Tan, and Cheng-Kok Koh. [slides]

12:30 – 2:00 pm: Lunch

2:00 – 3:30 pm Session 5: PD for Reliability and Adaptability

Session Chair: Shuai Li (Cadence)

(Invited) “Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue”, Julien Ryckaert (IMEC) [slides]

“Proximity Optimization for Adaptive Circuit Design”, Ang Lu, Hao He and Jiang Hu. [slides]

“Load-Aware Redundant Via Insertion for Electromigration Avoidance”, Steve Bigalke and Jens Lienig.

3:30 – 4:00 pm: Afternoon Break

4:00 – 6:00 pm Session 6: Commemoration for Prof. Ralph Otten

Session Chair: Michael Burstein (MediaBoost)

(Invited) “The Early Days of Automatic Floorplan Design”, Martin Wong (UIUC) [slides]

(Invited) “The Annealing Algorithm Revisited”, Lukas van Ginneken (DigiPen Institute of Technology) [slides]

(Invited) “Trailblazing Physical Design Flows: Ralph Otten's Impact on Design Automation”, Patrick Groeneveld (Synopsys) [slides]

(Invited) “Complexity and Diversity in IC Layout Design”, Ralph Otten (Technische Universiteit Eindhoven) [slides]


8:30 am – 10:10 am Session 7: FPGA Physical Design

Session Chair: Sabya Das (Xilinx)

(Invited) “An Interactive Physical Synthesis Methodology for High-frequency FPGA Designs”, Sabya Das, Rajat Aggarwal, Zhiyong Wang (Xilinx)

(Invited) “Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques”, Safeen Huda and Jason Anderson (Univ. of Toronto) [slides]

(Invited) “Scaling Up Physical Design: Challenges and Opportunities”, Guojie Luo, Wentai Zhang, Jiaxi Zhang (Peking Univ.), Jason Cong (UCLA) [slides]

(Invited) “Routability-Driven FPGA Placement Contest”, Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, Rajat Aggarwal (Xilinx) [slides]

10:10 – 10:30 am: Morning Break

10:30 am – 12:00 pm Session 8: Statistical and Machine Learning-Based CAD

Session Chair: Jackey Yan (Cadence)

“Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique”, Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango C.-T. Chao, Cheng-Hong Tsai, Yen-Chih Chiu. [slides]

“Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage”, Wei Wu, Srinivas Bodapati and Lei He. [slides]

“A Machine Learning Based Framework for Sub-Resolution Assist Feature Generation”, Xiaoqing Xu, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani and David Pan. [slides]

12:00 pm – 12:10 pm: Closing Remarks

12:10 – 1:30 pm: Lunch

1:30 – 5:30 pm: Social Activity