2014 International Symposium on Physical Design

With a Tribute to Dr Bryan Preas

Sheraton Sonoma County Petaluma, California, March 30-April 2, 2014

www.ispd.cc

Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS
Additional support from Altera, ATopTech, Cadence, IBM Research, ICScape, Intel, Mentor Graphics, Oracle, Synopsys, and Xilinx

 

 

PROGRAM

 

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas on the physical layout design of VLSI and biological systems. The scope of this symposium includes all aspects of physical design, from high-level interactions with logic synthesis, down to back-end performance optimization and design for manufacturing.

Regular presentations are 30 minutes.

 

SUNDAY, March 30

5:30 - 7:00 pm: Evening Reception

 

 

MONDAY, March 31

 

8:30 - 9:45 am: Welcome and Monday Keynote Address

Chair: Cliff Sze (IBM) [slides]

Keynote Talk: "Hardware Cyber Security", Serge Leef (Mentor Graphics) [slides]

9:45 - 10:15 am: Morning Break

 

10:15 am - 12:15 pm Session 1: Placement

Chair: Jackey Yan (Cadence)

"Cell Density-driven Detailed Placement with Displacement Constraint", Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai and Evangeline F. Y. Young (best paper candidate) [slides]

"MIP-based detailed placer for mixed-size circuits", Shuai Li and Cheng-Kok Koh
[slides]

"A Study on Unroutable Placement Recognition", Wen-Hao Liu, Tzu-Kai Chien and Ting-Chi Wang
[slides]

(Invited) "Integrated Structured Placement Design Methodology in Place and Route flow", Anand Arunachalam, (Synopsys)

 

 

12:15 – 1:45 pm: Lunch

 

1:45 – 3:15 pm Session 2: Routing

Chair: Igor Markov (University of Michigan)

“Timing-Driven, Over-the-Block Rectilinear Steiner Tree Construction with Pre-Buffering and Slew Constraints”, Yilin Zhang and David Pan. [slides]

“A Fast Algorithm for Rectilinear Steiner Trees with Length Restrictions on Obstacles”, Stephan Held and Sophie T. Spirkl. [slides]

(Invited) “FPGA Place & Route Challenges”, Rajat Aggarwal (Xilinx) [slides]

 

3:15 – 3:45 pm: Afternoon Break

 

3:45 – 5:15 pm Session 3: 3D Integration

Chair: Markus Olbrich (University of Hannover)

 

“Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs”, Shreepad Panth, Kambiz Samadi, Yang Du and Sung Kyu Lim (best paper candidate) [slides]

 

“Coupling-Aware Force Driven Placement of TSVs and Shields in 3D-IC layouts”, Caleb Serafy and Ankur Srivastava. [slides]

 

(Invited) “ 3DIC System Design Impact, Challenge and Solutions”, William (Bill) Wu Shen (TSMC) [slides]

 

6:00 – 8:00 pm: Monday Dinner Banquet

 

 

TUESDAY, April 1

 

8:30 – 9:30 am Tuesday Keynote Address

Chair: Patrick Groeneveld (Synopsys)

 

Keynote Talk: “Physical Design and FinFETs”, Rob Aitken (ARM R&D) [slides]

 

9:30 – 10:00 am: Morning Break

 

10:00 – 12:00 am Session 4: Clocking and Power-Grid Planning

Chair: Yu-Yen Mo (Oracle)

“Clock Tree Resynthesis for Multi-corner Multi-mode Timing Closure”, Subhendu Roy, Pavlos M. Mattheakis, David. Z. Pan and Laurent Masse-Navette (best paper candidate)  [slides]

“Power Optimization for Clock Network with Clock Gate Cloning and Flip-Flop Merging”, Mark Po-Hung Lin, Shih-Chuan Lo and Chih-Cheng Hsu.
[slides]

 

“Current Density Aware Power Switch Placement Algorithm for Power Gating Designs”, Jai Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai and Kevin Huang. [slides]

“Incremental Transient Simulation of Power Grid”, Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei and Liang-Chia Cheng.
[slides]

 

12:00 – 1:30 pm: Lunch

 

1:30 – 3:15 pm Session 5: DFM

Chair: Mustafa Ozdal (Intel)

 

“Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization”, Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu and David Z. Pan. [slides]

“A Highly-Efficient Row-Structure Stencil Planning Approach for E-Beam Lithography with Overlapped Characters”, Jian Kuang and Evangeline F.Y. Young.
[slides]

 

(Invited) “Carbon Nanotube Computer: Transforming Scientific Discoveries into Working Systems”, Subhasish Mitra (Stanford) [slides]

 

3:15 – 3:45 pm: Afternoon Break

 

3:45-5:15 pm Session 6: Commemoration for Dr. Bryan Preas

Chair: Cliff Sze (IBM) [slides]

 

“Making a Difference in EDA – A thank you to Bryan Preas for his contributions to the Profession”,  Michael Lorenzetti  (Mentor Graphics) [slides]

“From Design to Design Automation”, Jason Cong (UCLA) [slides]

 
“Interconnect Length Estimation in VLSI Designs: A Retrospective”, Massoud Pedram (USC)
[slides]

“Bryan Preas: Broad Contributions to System Engineering in the 2000's”, Scott Elrod  (PARC, a Xerox Company)
[slides]

 

6:00 – 8:30 pm: Tuesday Dinner Banquet

Chair: Cheng-Kok Koh (Purdue Univ.)

 

“Smart Matter Systems: An Introduction Through Examples”, Bryan Preas [slides]

 

WEDNESDAY, April 2

 

8:30 –10:30 am Session 7: CAD for Cyber Physical Systems

Chair: Dwight Hill (Synopsys)

“Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips”, Shang-Tsung Yu, Sheng-Han Yeh and Tsung-Yi Ho. [slides]

(Invited) “CAD for Automotive Embedded Systems”, Qi Zhu (UC Riverside) [slides]

(Invited) “Opportunities in Power Distribution Network System Optimization (from EDA Perspective)”, Gi-Joon Nam (IBM) [slides]

(Invited) “Indoor Localization Technology and Algorithm Issues”, Fan Ye (Peking University) [slides]

 

10:30 – 11:00 am: Morning Break

 

11:00 am – 12:15 pm Session 8: Contest

Chair: Bill Swartz (TimberWolf Systems)

 

(Invited) “The TAU 2014 Contest on Removing Common Path Pessimism During Timing Analysis”, Jin Hu (IBM), Debjit Sinha (IBM), Igor Keller (Cadence) [slides]

 

(Invited) “ISPD 2014 Benchmarks with Sub-45nm Technology Rules for Detailed Routing Driven Placement”, Vlad Yutsis (Mentor Graphics), Ismail Bustany (Mentor Graphics), David Chinnery (Mentor Graphics), Joseph Shinnerl (Mentor Graphics), and Wen-Hao Liu (NTHU) [slides]

 

12:15 – 12:30 pm: Closing Remarks

 

12:30 – 1:30 pm: Lunch