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ACM International Symposium on Physical Design

Doubletree Hotel, Monterey, California

April 6 - 9, 2003

www.ispd.cc

Sponsored by ACM/SIGDA with Technical Cosponsorship from IEEE CAS

Additional support from Cadence, IBM, Intel, Magma, Numerical Technologies, and Synopsys

FINAL PROGRAM

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas and results in critical areas related to the physical design of VLSI systems. The scope of this symposium includes all aspects of physical design, from interactions with behavior- and logic-level synthesis, to back-end performance analysis and verification.

April 1-4, Sonoma County CAwidth=
Sessions: [Keynote] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]

Foreword
Call for Papers - ISPD 2004
ISPD'03 Symposium Organization


Welcome and Keynote

Host: M. Pedram (University of Southern California)

Physical Design: The Whole Enchilada [p. 3]
R. Camposano (Synopsis Inc.)


Session 1: Placement and Physical Synthesis Deep Dive (invited)

Organizer: C. J. Alpert (IBM Corporation)

Important Placement Considerations for Modem VLSI Chips [p. 6]
P. Villarrubia (IBM Corporation), R. Vandarajan (Cadence Design Sys. Inc.)

Convergence of Placement Technology in Physical Synthesis: Is Placement really a point tool?
Ravi Varadarajan (Cadence Design Systems)


Session 2: Issues in Timing

Chair: M. Marek-Sadowska (University of California at Santa Barbara)

3D Thermal-ADI An Efficient Chip-Level Transient Thermal Simulator [p. 10]
T.-Y. Wang, Y.-M. Lee (Univ. of Wisconsin at Madison), C. C.-P. Chen (National Taiwan Univ.)

Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis [p. 18]
M. Hashimoto, Y. Yamada, H. Onodera (Kyoto University)
PowerPoint slides

Closed Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs [p. 24]
C. V. Kashyap, C. J. Alpert, F. Liu, A. Devgan (IBM Corporation)
PowerPoint slides

Explicit Gate Delay Model for Timing Evaluation [p. 32]
M. Shao (University of Texas at Austin), M. D. F. Wong (Univ. of Illinois at Urbana-Champaign), H. Cao (Motorola Inc.), Y. Gao, L.-P. Yuan (Synopsis Inc.), L.-D. Huang, S. Lee (University of Texas at Austin)
PowerPoint slides

Signal Integrity Management in an SoC Physical Design Flow [p. 39]
M. Becer, R. Vaidyanathan, C. Oh, R. Panda (Motorola Inc.)
PDF slides


Session 3: From the Trenches (invited)

Organizer & Chair: R. Rutenbar (Carnegie Mellon University)

There is Life Left in ASICs [p. 48]
L. Stok (IBM TJ Watson Research Center), J. Cohn (IBM Microelectronics)

The Scaling Challenge: Can Correct-by-Construction Design Help? [p. 51]
P. Saxena, N. Menezes, P. Cocchini, D. A. Kirkpatrick (Intel Labs)
PowerPoint slides


Session 4: Partitioning & Placement

Chair: P. Madden (SUNY Binghamton)

Timing Driven Force Directed Placement with Physical Net Constraints [p. 60]
K. Rajagopal (Intel Corporation), T. Shaked (Intel Corporation & University of Washington), Y. Parasuram, T. Cao, A. Chowdhary (Intel Corporation), B. Halpin (Intel Corporation & Syracuse University)

Fine Granularity Clustering for Large Scale Placement Problems [p. 67]
B. Hu, M. Marek-Sadowska (University of California at Santa Barbara)

Partition-Driven Standard Cell Thermal Placement [p. 76]
G. Chen (Synopsis Inc.), S. Sapatnekar (University of Minnesota)
PowerPoint slides

Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in Performance-Driven Bipartitioning [p. 81]
A. B. Kahng, X. Xu (University of California at San Diego)
PowerPoint slides


Session 5: Benchmarking

Chair: A. B. Kahng (University of California at San Diego)

Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms [p. 88]
J. Cong, M. Romesis, M. Xie (University of California at Los Angeles)
PowerPoint slides

Benchmarking For Large-scale Placement and Beyond [p. 95]
S. N. Adya (University of Michigan), M. C. Yildiz (SUNY Binghamton), I. L. Markov (University of Michigan), P. G. Villarrubia (IBM Corporation), P. N. Parakh (Monterey Design Systems), P. H. Madden (SUNY Binghamton)
PowerPoint slides


Session 6: Power Grid Design (invited)

Organizer & Chair: M. Pedram (University of Southern California)

A Complete Design for Power Methodology and Flow for Large ASICs [p. 106]
R. X. Nijssen, E. P. Huijbregts (Magma Design Automation)


Session 7: Lithography and Routing: What's Next? (invited)

Organizer & Chair: R. X. Nijssen (Magma Design Automation)

Layout Impact Resolution Enhancement Techniques: Impediment or Opportunity? [p. 110]
L. W. Liebmann (IBM Corporation)
PDF slides

Advanced Routing in Changing Technology Landscape [p. 118]
H. K.-S. Leung (Magma Design Automation)
PowerPoint slides

Research Directions for Coevolution of Rules and Routers [p. 122]
A. B. Kahng (University of California at San Diego)


Session 8: Floorplanning

Chair: C. C.-N. Chu (Iowa State)

Constrained "Modern" Floorplanning [p. 128]
Y. Feng, D. P. Mehta (Colorado School of Mines), H. Yang (Strategic CAD Labs., Intel)
PowerPoint slides

An Integrated Floorplanning with an Efficient Buffer Planning Algorithm [p. 136]
Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai (Tsinghua University), C. K. Cheng (University of California at San Diego), J. Gu (Science & Technology, University of Hong Kong)
PowerPoint slides

Floorplanning of Pipelined Array Modules using Sequence Pairs [p. 143]
M. Moe, H. Schmit (Carnegie Mellon University)
PowerPoint slides


Session 9: Routing and Clocking

Chair: P. Groeneveld (Eindhoven)

Efficient Steiner Tree Construction Based on Spanning Graphs [p. 152]
H. Zhou (Northwestern University)
PowerPoint slides

Porosity Aware Buffered Steiner Tree Construction [p. 158]
C. J. Alpert (IBM Corporation), G. Gandham (IBM Corporation at Hopewell Junction, NY), M. Hrkic (University of Illinois at Chicago), J. Hu (Texas A&M University), S. T. Quay (IBM Corporation)
PowerPoint slides

Epsilon-Optimal Minimum-Delay/Area Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time [p. 166]
J.-L. Tsai, T.-H. Chen (University of Wisconsin at Madison), C. C.-P. Chen (National Taiwan University)
PowerPoint slides

Process Variation Aware Clock Tree Routing [p. 174]
B. Lu (Cadence Design Sys. Inc.), J. Hu (Texas A&M University), G. Ellis (IBM Microelectronics), H. Su (IBM Austin Research Lab)
PowerPoint slides


Session 10: Regular Circuit Fabrics (invited)

Organizers: J. Cong (University of California at Los Angeles) and L. Pileggi (Carnegie Mellon University)
Chair: J. Cong (University of California at Los Angeles)

An Architectural Exploration of Via Patterned Gate Arrays [p. 184]
C. Patel, A. Cozzie, H. Schmit, L. Pileggi (Carnegie Mellon University)
PowerPoint slides

Architecture and Synthesis for Multi-Cycle Communication [p. 190]
J. Cong, Y. Fan, X. Yang, Z. Zhang (University of California at Los Angeles)

Synthesis and Placement Flow for Gain-Based Programmable Regular Fabrics [p. 197]
B. Hu, H. Jiang, Q. Liu, M. Marek-Sadowska (University of California at Santa Barbara)

Fishbone: A Block Level Placement and Routing Scheme [p. 204]
F. Mo, R. K. Brayton (University of California at Berkeley)
PowerPoint slides