The program below also links to the available slide presentations..

ACM/SIGDA 2002 INTERNATIONAL SYMPOSIUM ON PHYSICAL DESIGN

Hilton Hotel San Diego/Del Mar, Del Mar, California

April 7 - 10, 2002

www.ispd.cc

Sponsored by ACM SIGDA, in cooperation with the IEEE Circuits and Systems Society

Additional support from IBM, Intel, InTime Software, Magma Design Automation, Motorola,

Numerical Technologies, Silicon Perspective/Cadence and Synopsys

PROGRAM

The International Symposium on Physical Design provides a high-quality forum for the exchange of ideas and results in critical areas related to the physical design of VLSI systems. The scope of this symposium includes all aspects of physical design, from interactions with behavior- and logic-level synthesis, to back-end performance analysis and verification.

SUNDAY, APRIL 7

5:30 7:00 pm Evening Reception

MONDAY, APRIL 8

8:30 9:30 am Welcome and Keynote

Host: S. Sapatnekar

Keynote Address: S. Teig/Simplex

9:30 am 10:10 pm Session 1: Placement

Chair: F. Johannes/TU Munich

An Effective Congestion Driven Placement Framework
A. Rohe, U. Brenner
PowerPoint Slides

Consistent Placement of Macro-Blocks Using Floorplanning and Standard-Cell Placement
S. N. Adya, I. L. Markov
PowerPoint Slides

10:10 10:40 am Break

10:40 12:00 am Session 2: Panel - Do you have to get your whole physical solution from one company

Organizer and Moderator: D. Hill/Synopsys
Panelists: R. Camposano, Synopsys , W-J. Dai, Silicon Perspective, P. Hersher, Simplex, J. G. Xi, Plato, S. Young, Nassda

12:00 1:30 pm Lunch

1:30 2:30 pm Session 3: -- Leakage current

Chair: P. Groeneveld/Magma

Leakage Current in Low Threshold Devices: Trends and Challenges (invited)
Speaker: G. Yeap/Motorola

Leakage Current Control via Circuit Level and Layout Optimizations (invited)
Speaker: V. De/IBM

2:30 3:30 pm Session 4: Physical hierarchy
Chair: K. Bazargan/Minnesota

Design Hierarchy Guided Multilevel Circuit Partitioning
Y. Cheon, D.F. Wong
PowerPoint Slides

Physical Hierarchy Generation with Routing Congestion Control
C-C. Chang, J. Cong, D. Pan, X. Yuan
PowerPoint Slides

Routability Driven White Space Allocation for Fixed-die Standard-cell Placement
X. Yang, B-K. Choi, M. Sarrafzadeh
PowerPoint Slides

3:30 4:00 pm Break

4:00 5:20 pm Session 5: Floorplanning and post-layout optimization
Chair: H. Zhou/Northwestern

Routability Driven Floorplanner with Block Planning

S-C. Wing, Y-F. Yu

PowerPoint Slides

Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Microprocessor Designs

F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang,

N. Sherwani

TEG: A New Post-Layout Optimization Method

S. Zhang, W. Dai

PDF Slides

An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts

H. Su, S. Sapatnekar, S. R. Nassif

PDF Slides

TUESDAY, APRIL 9

9:00 9:50 am Session 6: Thermal issues

Chair: M. Pedram/USC

On-chip Thermal Engineering for Peta-scale Integration (invited)

Speaker: S. Kang/UCSC

9:50 am 10:30 pm Session 7: Crosstalk noise
Chair: M. Marek-Sadowska/UCSB
Shield Count Minimization in Congested Regions

P. Saxena, S. Gupta

PDF Slides

On Convergence of Switching Windows Computation in Presence of Crosstalk Noise

P. Chen, Y. Kukimoto, C-C. Teng, K. Keutzer

PowerPoint Slides

10:30 11:00 am Break

11:00 am 12:00 pm Session 8: Buffer insertion
Chair: J. Lou/Synopsys
Buffer Insertion with Adaptive Blockage Avoidance

J. Hu, C. J. Alpert, S. T. Quay, G. Gandham PowerPoint Slides

Buffer Tree Synthesis with Consideration of Temporal Locality, Sink Polarity Requirements, Solution Cost and Blockages

M. Hrkic, J. Lillis

Simultaneous Driver Sizing and Buffer Insertion Using a Delay Penalty Estimation Technique

C. J. Alpert, C-N. Chu, R. G. Gandham, M. Hrkic, J. Hu, C. Kashyap, S. T. Quay

PowerPoint Slides


12:00 1:30 pm Lunch

1:30 2:30 pm Session 9: Future design trends

Chair: C. J. Alpert/IBM

CMOS process trends, ITRS roadmap and visions for Physical Design (invited)

Speaker: A. B. Kahng/UCSD

PowerPoint Slides

Physical Design with Multiple On-chip Voltages (invited)

Speaker: C-H. Chen/Windsor

2:30 3:10 pm Session 10: Poster Paper Introductions

Chair: J. Lillis/UIC
Incremental Delay Change Due to Crosstalk Noise

L. H. Chen, M. Marek-Sadowska

PowerPoint Slides

Crosstalk Noise Optimization by Post-Layout Transistor Sizing

M. Hashimoto, M. Takahashi, H. Onodera

PowerPoint Slides

Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping

D. Pandini, L. T. Pileggi, A. J. Strojwas

PDF Slides

Smoothness and Uniformity of Filled Layout for VDSM Manufacturability

Y. Chen, G. Robins, A. Zelikovsky

PDF Slides

Min-Max Placement for Large-scale Timing Optimization

A. B. Kahng, S. Mantik, I. L. Markov

powerpoint

Global Clustering-Based Performance-Driven Circuit Partitioning

J. Cong, C. Wu

PowerPoint Slides

Net Criticality Revisited: An Effective Method to Improve Timing in Physical Design

H-L. Chang, E. Shragowitz, J. Liu, H. Youseff, B. Lu, S. Sutanthavibul

PowerPoint Slides

FAR: Fixed-Points Addition and Relaxation Based Placement

B. Hu, M. Marek-Sadowska

PowerPoint Slides


3:10 4:00 pm Poster Discussions

4:00 5:20 pm Session 11: Design Above the Silicon Surface: Package, Board and Beyond

Organizer and Moderator: R. A. Rutenbar/CMU

Speakers: K. Rinebold/Avant!, D. Wood/Intel

5:20 10:30 pm ISPD Tuesday Evening Event

WEDNESDAY, APRIL 10

9:00 9:50 am Session 12: Timing closure

Chair: M. Pedram/USC

Timing Closure Based on Physical Hierarchy (invited)

Speaker: J. Cong / UCLA

9:50 10:30 am Session 13: Routing

Chair: I. Markov/Michigan

Timing-Driven Routing for FPGAs Based on Largrangian Relaxation

S. Lee, D. F. Wong

PowerPoint Slides

sub-SAT: A Formulation for Relaxed Boolean Satisfiability with Applications in Routing

H. Xu, R.A. Rutenbar, K. Sakallah

10:30 11:00 am Break

11:00 am 12:00 pm Session 14: Topics in physical design

Chair: L. Scheffer/Cadence

Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning

W-K. Mak, F.Y. Young

PowerPoint Slides

Twin Binary Sequences: A Non-Redundant Representation for General Non-Slicing Floorplan

F.Y. Young, C.N. Chu, Z.C. Shen

PowerPoint Slides

Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis

L. Daniel, C.S. Ong, S. C. Low, K.H. Lee, J. White

PDF Slides

12:00 12:10 pm Closing Remarks

Symposium Organization

General Chair S. Sapatnekar (Minnesota)

Past Chair M. Wiesel

Steering Committee Chair M. Sarrafzadeh (UCLA)

Steering Committee D. Hill (Synopsys), A. B. Kahng (UCSD), R. A. Rutenbar (CMU),

M. Sarrafzadeh [Chair] (UCLA), D. F. Wong (Texas), M. Wiesel

Technical Program Chair M. Pedram (USC)

Technical Program Committee

C. J. Alpert (IBM) K. Banerjee (Stanford) K. Bazargan (Minnesota)

D. Blaauw (Michigan) C.-N. Chu (Iowa State) J. Cong (UCLA)

P. Groeneveld (Magma) F. Johanness (TUM) C-K. Koh (Purdue)

D. Kirkpatrick (Intel) J. Lillis (UIC) J. Lou (Synopsys)

M. Marek-Sadowska (UCSB) I. Markov (Michigan) H. Onodera (Kyoto)

S. Raje (Monterey) S. Sapatnekar (Minnesota) L. Scheffer (Cadence)

J. Soukup (Intime) H. Zhou (Synopsys)

Publication Chair C. J. Alpert (IBM)

Publicity Chair/Webmaster P. Groeneveld (Magma)

 


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