ISPD 2009 Clock Network Synthesis Contest
[News and Announcements].
[Evaluation and Ranking].
[Join the Contest].
[Terms and Conditions]
News and Announcements
- Apr 2, 2009 (THU): Results have been released two days ago in ISPD
2009. Thank you for everyone who helped me and who joined the contest. I
am sure all the participants learned a lot. In fact, some students
described it similar to an summer internship. My presentation of the
results can be downloaded here.
- Apr 2, 2009 (THU): I prepared a super zip file for everyone. Please
download the package. The package
contains: (1) 7 final benchmarks; (2) 4 extra benchmarks for your
entertainment; (3) latest eval2009.pl which generates more statistics; (4)
all CNS results from the final 9 teams; (5) all statistics I collected
from all CNS solution from all 9 teams for the final 7 benchmarks.
- Feb 23, 2009 (MON): Alpha version is due today! Please remember to
send me your alpha-version-executable today by 11:59p US Central Time (GMT-6).
- Feb 23, 2009 (MON): The deadline of final-version
submission has been extended to 3/11. Please note that this is a firm
deadline. On 3/11, you have to submit (1) your final-version-binary, and
(2) a one-page description of your algorithm.
- Feb 21, 2009 (SAT): 4 new samples have been released. The evaluation
script has also been updated with bug fixes. Please click here.
- Feb 21, 2009 (SAT): Another inverter type is released. Please note
that ALL benchmarks will use the two inverter types (clkinv0.subckt and
clkinv1.subckt) which can be found in the zip file bundled with the
evaluation script. Please click here.
- Feb 21, 2009 (SAT): The two Vdd setting to calculate
CLR will ALWAYS be 1V and 1.2V for all benchmarks.
- Feb 01, 2009 (SUN): FAQ has been updated! Please read this faq.txt.
- Feb 01, 2009 (SUN): the evaluation script eval2009.pl has been
updated. Please download the latest script at here. Except necessary bug fixes, we should expect
this is final version of the evaluation script, which will be used to
rank your clock network synthesis tool. Change log:
- bug fixes: (1) Blockage reading. (2) Adding inverter at source
makes source's coordinate (-1,-1).
added handling of the 15-column reporting of ngspice for 14+
- added long interconnect segmentation for interconnects longer than
500um. This is to account for the "shielding effect of the
- Feb 01, 2009 (SUN): the sample testcase (s1, s1s) has been updated.
Please download the latest sample testcase at
here. Change log:
- Buffer type at source was wrong. Fixed.
- Buffer output resistance has been added together with input load
capacitance and output parasitic capacitance. This is to make the
switch RC model complete. However, I do not recommend relying these
three numbers to optimize CLR.
- Jan 26, 2009 (MON): I sent an email today in order to check
everyone is on my mailing list. If you are a participant but did not
receive my email, please let me know as soon as possible. I am going to
update the evaluation script eval2009.pl and the sample testcase (s1, s1s)
this week to fix some bugs.
- Jan 25, 2009 (SUN): Finally, 26 teams joined the contest. Please see
- Jan 18, 2009 (SUN): I cut-and-paste all the questions from different
teams and publish a FAQ. Please see this faq.txt.
- Jan 18, 2009 (SUN): So far, 19 teams all over the world has
registered. Please see the list.
- Jan 08, 2009 (THU): This site is updated with
detailed rules and terms. A sample testcase and a script to run ngspice
simulation are also provided. The files are bundled as a starter
- Dec 29, 2008 (MON): A link with detailed contest information has been
provided to individuals who have sent emails to me for registration or
questions. The contest details will be finalized and posted in this
website before Jan 8, 2009 together with sample benchmarks and scripts.
- Dec 21, 2008 (SUN): The deadline of participation registration will
be moved to January 21, 2009.
- Nov 16, 2008 (SUN): Please note that the organization team is still
working on the benchmarks. The dates in "CFP" will be revised accordingly.
The release of benchmark may be postponed by 2 weeks.
- Nov 02, 2008 (SUN): Webpage is created announcing the new contest.
Continuing the tradition of spirited competition, the ISPD 2009 Steering Committee is pleased to
announce a clock distribution network synthesis contest. Like the prior
placement and routing contests, a set of benchmarks will be released; teams
are invited to produce clock distribution network solutions, with the best
results winning fame, recognition, and a grand prize.
Call for Participation
For the contest announcement and call for participation, please see
Nov 02, 2008: Announcement of the Contest
Jan 21, 2009: Last day to confirm participation with Dr. Cliff Sze (firstname.lastname@example.org).
Feb 23, 2009: Each team must submit an alpha-version executable and a
script to test running it on our platforms. This is very important to make
sure that our simulation results match yours.
Mar 11, 2009: Final day to submit the final-version binary for your clock
tools, and results. (Time: 23:59 CST, UTC-6). A one-page description of
your algorithm must be attached with your final submission.
Mar 31, 2009: ISPD 2009 results release and prizes giving
Tool Evaluation and Ranking
We will use the open-sourced ngspice to simulate your clock distribution
network and calculate the clock latency. Please download ngspice from here and compile it in your own
system. You have to download the source code (the download filename must be
ng-spice-rework-17.tar.gz or ng-spice-rework-18.tar.gz. Since a lot
students cannot find the link, here we provide
the source download link.
After you un-tar the package, you can find the documentation at
"ng-spice-rework-18/doc/ngspice.pdf". You have to make sure how to use this
simulator because you may need to try your solution (or subsets of your
clock distribution network) without using the official script.
- The contest will base on 45nm technology. We will use the PTM model card
with minimal change to be used in the ngspice environment. For more
information about PTM, please visit their official website at here.
We assume the clock source is at (0,0) which is the bottom left corner.
We assume an inverter will be placed exactly at clock source. The example
spice model of the inverter is here and it is
based on this model card. Using this two
files by the command "ngspice -b clkinv1.spice", you will get this result. The corresponding plot will look like this.
The clock source inverter will be "automatically" added by the translator
script. So, your tool can assume an inverted signal from the source (driven
by the inverter). The inserted clock source inverter will be defined in
the input file. The input slew to this clock source inverter is always
We will provide a couple buffer/inverter types for constructing the clock
distribution network. The buffer/inverter type will be similar to this(the .subckt part). Of course, you can connect
more than one inverter in parallel and the structure will give you a higher
drive strength. A figure of parallel connected inverters can be found here.
The clock distribution network does not have to be a tree. Once again,
buffers/inverter connected in parallel, or mesh/grid/cross-link structures
are allowed. Of course, you can connect two nodes with more than one wire
in parallel to reduce the resultant wire resistance. However, we enforce a
power-limit to all the solutions. Examples of inverters-in-parallel and
wires-in-parallel can be found in the sample output file "s1s" inside the
We assume the clock frequency is 2GHz with clock period of 500ps. Slew
(10%-90%) limit is 100ps.
We will provide a translator to convert from the output file format to
spice input file. The interconnect will be formulated with Pi-model. Long
interconnect will be segmented in advance.
Two type of wires will be available: wide wire (0.1 Ohms/um, 0.2 fF/um),
narrow wire (0.3 Ohms/um, 0.16 fF/um).
The clock signal arriving the clock sinks must be "non-inverted". In other
words, there must be even number of inverters along the path from the clock
source to each clock sink. This is including the compulsory single inverter
we add to the clock source.
There are placement blockages in the layout while there are NO wiring
blockages. In other words, no buffer/inverter can be placed on top of any
blockage we provided but routing can be done over it.
Buffer/inverter placement will be formulated as a "point", which is a
single x,y location. This represents the buffer input/output pins. As a
result, the input pin and output pin must have the same coordinates when
you route the input/output nets of the buffer/inverter. Since the
buffer/inverter placement model is a point, you only have to make sure such
point is not covered by any placement blockage provided.
We will account for process variation in this contest. Usually, Monte
Carlo simulation will be used. However, it is too time-consuming to do
Monte Carlo simulation for all teams and all benchmarks. Instead, we will
use a simple method to test the robustness of each clock distribution
network solution. Two SPICE simulations will be
done to each clock network solution with different Vdd settings (e.g. 1V
and 1.1V). The team with smallest range of clock latency across
different simulations will win. In this contest, we will use the term
"clock latency range" (CLR).
For example, assume there are 3 clock sinks (S1,S2,S3) in the clock network.
On 1V, the clock latency of S1,S2,S3 are 13,15,12. On 1.1V supply voltage,
the clock latency of S1,S2,S3 are 7,9,8. Then, the CLR = 15-7 = 8.
CLR is different from clock skew. In this example, clock skew on 1V is
15-12=3 while clock skew on 1.1V is 2. In other words, a solution with
larger clock skew but with smaller CLR will still win the contest. For
example, if another solution produce clock latency of 11,16,15 on 1V and
11,13,12 on 1.1V. This solution is better than the previous one because the
CLR is 16-11=5 even though it has bigger clock skew (5 on 1V) and larger
worst-case clock latency.
For each benchmark, a list of voltage settings will be provided in the input
There will be a power limit for each benchmark. Although using I,V curve
from SPICE simulation to estimate power would be more accurate, it is
easier and faster to use the CVVf equation to estimate average power. As a
result, we will use total interconnect and inverter capacitance as a
measurement of power. We will provide a total capacitance limit in the
input file of each benchmark.
For each inverter type, we will provide the input capacitance and output
parasitic capacitance for total capacitance calculation. All the
information will be provided in the input file.
The clock distribution network solutions will be evaluated on the following
The final rank of a clock network synthesis tool will be determined by the sum of
individual ranks of circuits. The smallest rank number wins the contest.
For each benchmark, the solution with no slew violation, with no power
violation (in terms of capacitance limit), and with smallest CLR will win.
If two solutions have the same CLR value, we will use power(i.e. total
capacitance) as the tie-breaker.
If two solutions have the same CLR value and the same total capacitance, we
will use CPU-time as the second tie-breaker. CPU-time is the total running
time of your clock network synthesis tool in our dedicated Linux machine.
Since we only have 2 weeks to run all clock network synthesis tool and we have more than 10
participating teams. The runtime limit is set to 24
hours. If a clock network synthesis tool executable takes more than 24
hours to complete a benchmark, it is consider to be failed.
We work hard to make sure the input/output format is as simple as possible.
The detailed description of the input/output format can be found in this
Small sample input/output files
Here are a sample input file and a sample output file of a simple 4-sink
clock network synthesis problem, with illustrations.
Join the Contest
If you are interested in participating in the contest, or even if you
have any question, please feel free to send an email to Dr. Cliff Sze (email@example.com).
To ensure prompt response, please start with "ISPD2009-CTS" in the subject of your email.
Final submission time is set to (Mar 11) 11:59pm CST, which is in different
time zone as, for example,
9:59pm (Mar 1) in California,
1:59pm (Mar 2) in Beijing, Taipei and Hong Kong,
6:59am (Mar 2) in Hannover, Germany.
You can send me an http-link such that I can download your binary (or source
files), scripts, clock network synthesis result files and a one-page algorithm
description from the link. Please zipped or gtar all files.
Terms and Conditions
The contest is sponsored by IEEE CEDA.