April 14 - 17, 2019
San Francisco, California, USA

Symposium Program

A printable version (PDF) of the technical program can be downloaded here.

Sunday, April 14

5:30pm - 7:00pm: Reception

Monday, April 15

7:45am - 8:45am: Breakfast

8:45am - 9:00am: General Chair Welcome Message

9:00am - 10:00am: Keynote “Fusion: The Dawn of the Hyperconvergence Era in EDA”, Shankar Krishnamoorthy

10:00am - 10:30am: Morning Break

10:30am - 12:30pm: New Approaches in Placement

“How Deep Learning Can Drive Physical Synthesis Towards more Predictable Legalization”, Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius Livramento, Laercio Pilla, Jose Luis Guntzel

“Graceful Register Clustering by Effective Mean Shift Algorithm for Balancing Power and Timing”, Ya Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang, Gi-Joon Nam

“Device Layer-Aware Analytical Placement for Analog Circuits”, Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Pan

“Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization”, Xingquan Li, Jianli Chen, Wenxing Zhu, YaoWen Chang

12:30pm - 2:00pm: Lunch

2:00pm - 3:30pm: FPGA Special Session: Advances in Adaptable Heterogenenous Computing and Acceleration for Big Data

“FPGA-based Computing in the Era of Artificial Intelligence and Big Data”, Eriko Nurvitadhi

“Advances in Adaptable Computing”, Amit Gupta

“Improving Efficiency and Programmability of Large-Scale Graph Analytics for FPGA Platforms”, Mustafa Ozdal

3:30pm - 4:00pm: Afternoon break

4:00pm - 6:00pm: Routing in All Forms

“Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints”, Nikolay Ryzhenko, Steven Burns, Anton Sorokin, Mikhail Talalay

“PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs”, Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, Jose Alves, Ulf Schlichtmann

“Construction of All Multilayer Monolithic Recti-linear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing”, Sheng-En David Lin, Dae Hyun Kim

“RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques”, Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng

6:30pm - 9:00pm: Dinner and Social Event

Tuesday, April 16

7:45am - 8:45am: Breakfast

9:00am - 10:00am: Keynote

“A Perspective on Security and Trust Requirements for the Future”, Ken Plaks

10:00am - 10:30am: Morning Break

10:30am - 12:30pm: Patterning and Machine Learning

“Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling”, Gyuszi Suto, Geoff Greenleaf, Sanjay Soni, Heinrich Fischer, Phanindra Bhagavatula, Renato Hentschke, Brian Miller

“Electromigration-aware Interconnect Design”, Sachin S. Sapatnekar

“Toward Intelligent Physical Design: Deep Learning and GPU Acceleration”, Haoxing Ren

“Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement”, Hua-Yu Chang, Iris Hui-Ru Jiang

12:30pm - 2:00pm: Lunch

2:00pm - 3:30pm: Cyber Physical Systems Session

“From Electronic Design Automation to Automotive Design Automation”, Chung-Wei Lin

“Enterprise-wide AI-enabled Digital Transformation”, Mehdi Maasoumy

“Secure and Trustworthy Cyber-Physical System Design: A Cross-Layer Perspective”, Pierluigi Nuzzo

3:30pm - 4:00pm: Afternoon break

4:00pm - 5:30pm: Tribute to Professor Alberto Sangiovanni Vicentelli

“The Slow Start of Fast Spice: a Brief History of Timing”, Jacob White

“Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions”, Masahiro Fujita

“From Electronic Design Automation to CyberPhysical System Design Automation: A Tale of Platform-Based Design”, Pierluigi Nuzzo

“My 50-Year Journey from Punched Cards to Swarm Systems”, Alberto Sangiovanni-Vincentelli

6:00pm - 8:30pm: Lifetime Achievement Award Dinner Banquet

Wednesday, April 17

7:45am - 8:45am: Breakfast

8:45am - 10:15am: Physical Design - Where are we going?

“Analog Layout Synthesis: Are we there yet?”, Prasanth Mangalagiri

“Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach”, Ankur Sharma, David Chinnery, Chris Chu

“Adaptive Clustering and Sampling for HighDimensional and Multi-Failure-Region SRAM Yield Analysis”, Xiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi, Lei He

10:15am - 10:30pm: Morning Break

10:30am - 12:00pm: Routing Contest

Session chair : TBA

“ISPD 2019 Initial Detailed Routing Contest and Benchmarks”, Gracieli Posser

12:00pm - 1:00pm: Lunch

1:00pm - 1:45pm: Poster Session

1:45pm - 3:00pm: Special Session and Closing Remarks

3:30pm - 5:30pm: Social Event

Best Paper Award candidates

  1 Nikolay Ryzhenko, Steven Burns, Anton Sorokin and Mikhail Talalay Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
  2 Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun and David Pan Device Layer-Aware Analytical Placement for Analog Circuits
  3 Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius Livramento, Laércio Pilla and Jose Luís Güntzel How Deep Learning Can Drive Physical Synthesis Towards more Predictable Legalization

Accepted Papers

  1 Nikolay Ryzhenko, Steven Burns, Anton Sorokin and Mikhail Talalay Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
  2 Gyuszi Suto, Geoff Greenleaf, Sanjay Soni, Heinrich Fischer, Phanindra Bhagavatula, Renato Hentschke and Brian Miller Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling
  3 Ankur Sharma, David Chinnery and Chris Chu Lagrangian Relaxation Based Gate Sizing with Clock Skew Scheduling - A Fast and Effective Approach
  4 Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Alves and Ulf Schlichtmann PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs
  5 Xiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi and Lei He Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis
  6 Sheng-En David Lin and Dae Hyun Kim Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing
  7 Xingquan Li, Jianli Chen, Wenxing Zhu and Yao-Wen Chang Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization
  8 Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun and David Pan Device Layer-Aware Analytical Placement for Analog Circuits
  9 Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin and Chung-Kuan Cheng RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques
  10 Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang and Gi-Joon Nam Graceful Register Clustering by Effective Mean Shift Algorithm for Balancing Power and Timing
  11 Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius Livramento, Laércio Pilla and Jose Luís Güntzel How Deep Learning Can Drive Physical Synthesis Towards more Predictable Legalization
  12 Hua-Yu Chang and Iris Hui-Ru Jiang Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement