March 25 - 28, 2018
Monterey, California, USA

Paper Submission
Easy Chair Submission

General Information

The International Symposium on Physical Design provides a premier forum to exchange ideas and promote research on critical areas related to the physical design of VLSI systems. All aspects of physical design, including its interactions with architecture, behavioral- and logic-level synthesis, and back-end performance analysis and verification are within the scope of the symposium. Target domains include semi-custom and full-custom ICs, regular fabrics, FPGAs, and systems-on-chip / systems-in-package. Following its twenty-six predecessors, the 2018 symposium will highlight new key directions and leading-edge theoretical and experimental contributions to the field. The ACM Press will publish accepted papers in the Symposium proceedings.
The symposium will pay a tribute to Professor Te C. Hu.
EE Times Coverage of ISPD 2017:    ISPD Predicts Chip Futures    Intel Shows Life Beyond CMOS

Accepted Papers

J. Hu, Y. Zhou, Y. Wei, S. Quay, L. Reddy, G. Tellez, G.-J. Nam
Interconnect Optimization Revisited
A. B. Kahng, C. Moyes, S. Venkatesh, L. Wang
Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics
C. J. Alpert, W.-K. Chow, K. Han, A. B. Kahng, Z. Li, D. Liu, S. Venkatesh
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees
S.-E. D. Lin, D. H. Kim
Construction of All Rectilinear Steiner Minimum Tree on the Hanan Grid
A. Lvov, G. Tellez, G.-J. Nam
On Triple and Quadruple Coloring of Integrated Circuits Shapes Layouts
Y. Lin, Y. Watanabe, T. Kimura, T. Matsunawa, S. Nojima, M. Li, D. Z. Pan
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning
R. Viera, P. Maurine, J.-M. Dutertre, R. P. Bastos
Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits
B. W. Ku, K. Chang, S. K. Lim
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
B. Xu, B. Basaran, M. Su, D. Z. Pan
Towards Layout Mining: Analog Placement Constraint Exploration with the Application to Layout Retargeting
W.-S. Kuo, S.-H. Zhang, W.-K. Mak, R. Sun, Y. K. Leow
Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
W. Ye, M. Li, K. Zhong, B. Yu, D. Z. Pan
Power Grid Reduction by Sparse Convex Optimization

Important Dates

Camera-ready paper dueJanuary 11, 2018
SymposiumMarch 25-28, 2018

Author Information

Publishing guidelinesSheridan publishing


Sponsored by ACM/SIGDA with Technical Co-Sponsorship from IEEE CAS. Additional support from: